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150
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1 // RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
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2 // Check if it is valid MCSchedClassDesc if didn't have the resources.
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3
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4 include "llvm/Target/Target.td"
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5
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6 def MyTarget : Target;
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7
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8 let OutOperandList = (outs), InOperandList = (ins) in {
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9 def Inst_A : Instruction;
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10 def Inst_B : Instruction;
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11 }
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12
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13 let CompleteModel = 0 in {
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14 def SchedModel_A: SchedMachineModel;
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15 def SchedModel_B: SchedMachineModel;
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16 def SchedModel_C: SchedMachineModel;
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17 }
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18
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19 // Inst_B didn't have the resoures, and it is invalid.
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20 // CHECK: SchedModel_ASchedClasses[] = {
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21 // CHECK: {DBGFIELD("Inst_A") 1
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207
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22 // CHECK-NEXT: {DBGFIELD("Inst_B") 8191
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150
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23 let SchedModel = SchedModel_A in {
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24 def Write_A : SchedWriteRes<[]>;
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25 def : InstRW<[Write_A], (instrs Inst_A)>;
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26 }
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27
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28 // Inst_A didn't have the resoures, and it is invalid.
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29 // CHECK: SchedModel_BSchedClasses[] = {
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207
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30 // CHECK: {DBGFIELD("Inst_A") 8191
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150
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31 // CHECK-NEXT: {DBGFIELD("Inst_B") 1
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32 let SchedModel = SchedModel_B in {
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33 def Write_B: SchedWriteRes<[]>;
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34 def : InstRW<[Write_B], (instrs Inst_B)>;
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35 }
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36
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37 // CHECK: SchedModel_CSchedClasses[] = {
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38 // CHECK: {DBGFIELD("Inst_A") 1
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39 // CHECK-NEXT: {DBGFIELD("Inst_B") 1
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40 let SchedModel = SchedModel_C in {
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41 def Write_C: SchedWriteRes<[]>;
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42 def : InstRW<[Write_C], (instrs Inst_A, Inst_B)>;
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43 }
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44
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45 def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
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46 def ProcessorB: ProcessorModel<"ProcessorB", SchedModel_B, []>;
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47 def ProcessorC: ProcessorModel<"ProcessorC", SchedModel_C, []>;
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