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1 //===- ExecutionDomainFix.cpp - Fix execution domain issues ----*- C++ -*--===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 #include "llvm/CodeGen/ExecutionDomainFix.h"
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11 #include "llvm/CodeGen/MachineRegisterInfo.h"
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12 #include "llvm/CodeGen/TargetInstrInfo.h"
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13
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14 using namespace llvm;
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15
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16 #define DEBUG_TYPE "execution-deps-fix"
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17
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18 iterator_range<SmallVectorImpl<int>::const_iterator>
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19 ExecutionDomainFix::regIndices(unsigned Reg) const {
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20 assert(Reg < AliasMap.size() && "Invalid register");
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21 const auto &Entry = AliasMap[Reg];
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22 return make_range(Entry.begin(), Entry.end());
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23 }
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24
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25 DomainValue *ExecutionDomainFix::alloc(int domain) {
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26 DomainValue *dv = Avail.empty() ? new (Allocator.Allocate()) DomainValue
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27 : Avail.pop_back_val();
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28 if (domain >= 0)
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29 dv->addDomain(domain);
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30 assert(dv->Refs == 0 && "Reference count wasn't cleared");
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31 assert(!dv->Next && "Chained DomainValue shouldn't have been recycled");
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32 return dv;
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33 }
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34
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35 void ExecutionDomainFix::release(DomainValue *DV) {
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36 while (DV) {
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37 assert(DV->Refs && "Bad DomainValue");
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38 if (--DV->Refs)
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39 return;
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40
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41 // There are no more DV references. Collapse any contained instructions.
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42 if (DV->AvailableDomains && !DV->isCollapsed())
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43 collapse(DV, DV->getFirstDomain());
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44
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45 DomainValue *Next = DV->Next;
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46 DV->clear();
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47 Avail.push_back(DV);
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48 // Also release the next DomainValue in the chain.
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49 DV = Next;
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50 }
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51 }
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52
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53 DomainValue *ExecutionDomainFix::resolve(DomainValue *&DVRef) {
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54 DomainValue *DV = DVRef;
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55 if (!DV || !DV->Next)
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56 return DV;
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57
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58 // DV has a chain. Find the end.
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59 do
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60 DV = DV->Next;
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61 while (DV->Next);
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62
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63 // Update DVRef to point to DV.
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64 retain(DV);
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65 release(DVRef);
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66 DVRef = DV;
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67 return DV;
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68 }
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69
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70 void ExecutionDomainFix::setLiveReg(int rx, DomainValue *dv) {
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71 assert(unsigned(rx) < NumRegs && "Invalid index");
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72 assert(!LiveRegs.empty() && "Must enter basic block first.");
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73
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74 if (LiveRegs[rx] == dv)
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75 return;
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76 if (LiveRegs[rx])
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77 release(LiveRegs[rx]);
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78 LiveRegs[rx] = retain(dv);
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79 }
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80
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81 void ExecutionDomainFix::kill(int rx) {
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82 assert(unsigned(rx) < NumRegs && "Invalid index");
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83 assert(!LiveRegs.empty() && "Must enter basic block first.");
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84 if (!LiveRegs[rx])
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85 return;
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86
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87 release(LiveRegs[rx]);
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88 LiveRegs[rx] = nullptr;
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89 }
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90
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91 void ExecutionDomainFix::force(int rx, unsigned domain) {
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92 assert(unsigned(rx) < NumRegs && "Invalid index");
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93 assert(!LiveRegs.empty() && "Must enter basic block first.");
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94 if (DomainValue *dv = LiveRegs[rx]) {
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95 if (dv->isCollapsed())
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96 dv->addDomain(domain);
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97 else if (dv->hasDomain(domain))
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98 collapse(dv, domain);
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99 else {
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100 // This is an incompatible open DomainValue. Collapse it to whatever and
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101 // force the new value into domain. This costs a domain crossing.
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102 collapse(dv, dv->getFirstDomain());
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103 assert(LiveRegs[rx] && "Not live after collapse?");
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104 LiveRegs[rx]->addDomain(domain);
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105 }
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106 } else {
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107 // Set up basic collapsed DomainValue.
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108 setLiveReg(rx, alloc(domain));
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109 }
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110 }
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111
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112 void ExecutionDomainFix::collapse(DomainValue *dv, unsigned domain) {
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113 assert(dv->hasDomain(domain) && "Cannot collapse");
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114
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115 // Collapse all the instructions.
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116 while (!dv->Instrs.empty())
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117 TII->setExecutionDomain(*dv->Instrs.pop_back_val(), domain);
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118 dv->setSingleDomain(domain);
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119
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120 // If there are multiple users, give them new, unique DomainValues.
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121 if (!LiveRegs.empty() && dv->Refs > 1)
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122 for (unsigned rx = 0; rx != NumRegs; ++rx)
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123 if (LiveRegs[rx] == dv)
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124 setLiveReg(rx, alloc(domain));
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125 }
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126
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127 bool ExecutionDomainFix::merge(DomainValue *A, DomainValue *B) {
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128 assert(!A->isCollapsed() && "Cannot merge into collapsed");
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129 assert(!B->isCollapsed() && "Cannot merge from collapsed");
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130 if (A == B)
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131 return true;
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132 // Restrict to the domains that A and B have in common.
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133 unsigned common = A->getCommonDomains(B->AvailableDomains);
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134 if (!common)
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135 return false;
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136 A->AvailableDomains = common;
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137 A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
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138
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139 // Clear the old DomainValue so we won't try to swizzle instructions twice.
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140 B->clear();
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141 // All uses of B are referred to A.
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142 B->Next = retain(A);
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143
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144 for (unsigned rx = 0; rx != NumRegs; ++rx) {
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145 assert(!LiveRegs.empty() && "no space allocated for live registers");
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146 if (LiveRegs[rx] == B)
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147 setLiveReg(rx, A);
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148 }
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149 return true;
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150 }
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151
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152 void ExecutionDomainFix::enterBasicBlock(
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153 const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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154
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155 MachineBasicBlock *MBB = TraversedMBB.MBB;
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156
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157 // Set up LiveRegs to represent registers entering MBB.
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158 // Set default domain values to 'no domain' (nullptr)
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159 if (LiveRegs.empty())
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160 LiveRegs.assign(NumRegs, nullptr);
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161
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162 // This is the entry block.
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163 if (MBB->pred_empty()) {
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164 DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n");
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165 return;
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166 }
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167
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168 // Try to coalesce live-out registers from predecessors.
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169 for (MachineBasicBlock *pred : MBB->predecessors()) {
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170 assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() &&
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171 "Should have pre-allocated MBBInfos for all MBBs");
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172 LiveRegsDVInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];
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173 // Incoming is null if this is a backedge from a BB
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174 // we haven't processed yet
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175 if (Incoming.empty())
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176 continue;
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177
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178 for (unsigned rx = 0; rx != NumRegs; ++rx) {
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179 DomainValue *pdv = resolve(Incoming[rx]);
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180 if (!pdv)
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181 continue;
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182 if (!LiveRegs[rx]) {
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183 setLiveReg(rx, pdv);
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184 continue;
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185 }
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186
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187 // We have a live DomainValue from more than one predecessor.
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188 if (LiveRegs[rx]->isCollapsed()) {
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189 // We are already collapsed, but predecessor is not. Force it.
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190 unsigned Domain = LiveRegs[rx]->getFirstDomain();
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191 if (!pdv->isCollapsed() && pdv->hasDomain(Domain))
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192 collapse(pdv, Domain);
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193 continue;
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194 }
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195
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196 // Currently open, merge in predecessor.
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197 if (!pdv->isCollapsed())
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198 merge(LiveRegs[rx], pdv);
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199 else
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200 force(rx, pdv->getFirstDomain());
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201 }
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202 }
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203 DEBUG(dbgs() << printMBBReference(*MBB)
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204 << (!TraversedMBB.IsDone ? ": incomplete\n"
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205 : ": all preds known\n"));
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206 }
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207
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208 void ExecutionDomainFix::leaveBasicBlock(
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209 const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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210 assert(!LiveRegs.empty() && "Must enter basic block first.");
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211 unsigned MBBNumber = TraversedMBB.MBB->getNumber();
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212 assert(MBBNumber < MBBOutRegsInfos.size() &&
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213 "Unexpected basic block number.");
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214 // Save register clearances at end of MBB - used by enterBasicBlock().
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215 for (DomainValue *OldLiveReg : MBBOutRegsInfos[MBBNumber]) {
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216 release(OldLiveReg);
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217 }
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218 MBBOutRegsInfos[MBBNumber] = LiveRegs;
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219 LiveRegs.clear();
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220 }
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221
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222 bool ExecutionDomainFix::visitInstr(MachineInstr *MI) {
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223 // Update instructions with explicit execution domains.
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224 std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(*MI);
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225 if (DomP.first) {
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226 if (DomP.second)
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227 visitSoftInstr(MI, DomP.second);
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228 else
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229 visitHardInstr(MI, DomP.first);
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230 }
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231
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232 return !DomP.first;
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233 }
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234
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235 void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) {
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236 assert(!MI->isDebugValue() && "Won't process debug values");
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237 const MCInstrDesc &MCID = MI->getDesc();
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238 for (unsigned i = 0,
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239 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
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240 i != e; ++i) {
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241 MachineOperand &MO = MI->getOperand(i);
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242 if (!MO.isReg())
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243 continue;
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244 if (MO.isUse())
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245 continue;
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246 for (int rx : regIndices(MO.getReg())) {
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247 // This instruction explicitly defines rx.
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248 DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << *MI);
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249
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250 // Kill off domains redefined by generic instructions.
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251 if (Kill)
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252 kill(rx);
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253 }
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254 }
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255 }
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256
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257 void ExecutionDomainFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
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258 // Collapse all uses.
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259 for (unsigned i = mi->getDesc().getNumDefs(),
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260 e = mi->getDesc().getNumOperands();
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261 i != e; ++i) {
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262 MachineOperand &mo = mi->getOperand(i);
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263 if (!mo.isReg())
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264 continue;
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265 for (int rx : regIndices(mo.getReg())) {
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266 force(rx, domain);
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267 }
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268 }
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269
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270 // Kill all defs and force them.
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271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
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272 MachineOperand &mo = mi->getOperand(i);
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273 if (!mo.isReg())
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274 continue;
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275 for (int rx : regIndices(mo.getReg())) {
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276 kill(rx);
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277 force(rx, domain);
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278 }
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279 }
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280 }
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281
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282 void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
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283 // Bitmask of available domains for this instruction after taking collapsed
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284 // operands into account.
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285 unsigned available = mask;
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286
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287 // Scan the explicit use operands for incoming domains.
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288 SmallVector<int, 4> used;
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289 if (!LiveRegs.empty())
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290 for (unsigned i = mi->getDesc().getNumDefs(),
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291 e = mi->getDesc().getNumOperands();
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292 i != e; ++i) {
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293 MachineOperand &mo = mi->getOperand(i);
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294 if (!mo.isReg())
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295 continue;
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296 for (int rx : regIndices(mo.getReg())) {
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297 DomainValue *dv = LiveRegs[rx];
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298 if (dv == nullptr)
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299 continue;
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300 // Bitmask of domains that dv and available have in common.
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301 unsigned common = dv->getCommonDomains(available);
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302 // Is it possible to use this collapsed register for free?
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303 if (dv->isCollapsed()) {
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304 // Restrict available domains to the ones in common with the operand.
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305 // If there are no common domains, we must pay the cross-domain
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306 // penalty for this operand.
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307 if (common)
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308 available = common;
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309 } else if (common)
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310 // Open DomainValue is compatible, save it for merging.
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311 used.push_back(rx);
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312 else
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313 // Open DomainValue is not compatible with instruction. It is useless
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314 // now.
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315 kill(rx);
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316 }
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317 }
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318
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319 // If the collapsed operands force a single domain, propagate the collapse.
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320 if (isPowerOf2_32(available)) {
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321 unsigned domain = countTrailingZeros(available);
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322 TII->setExecutionDomain(*mi, domain);
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323 visitHardInstr(mi, domain);
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324 return;
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325 }
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326
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327 // Kill off any remaining uses that don't match available, and build a list of
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328 // incoming DomainValues that we want to merge.
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329 SmallVector<int, 4> Regs;
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330 for (int rx : used) {
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331 assert(!LiveRegs.empty() && "no space allocated for live registers");
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332 DomainValue *&LR = LiveRegs[rx];
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333 // This useless DomainValue could have been missed above.
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334 if (!LR->getCommonDomains(available)) {
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335 kill(rx);
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336 continue;
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337 }
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338 // Sorted insertion.
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339 // Enables giving priority to the latest domains during merging.
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340 auto I = std::upper_bound(
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341 Regs.begin(), Regs.end(), rx, [&](int LHS, const int RHS) {
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342 return RDA->getReachingDef(mi, RC->getRegister(LHS)) <
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343 RDA->getReachingDef(mi, RC->getRegister(RHS));
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344 });
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345 Regs.insert(I, rx);
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346 }
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347
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348 // doms are now sorted in order of appearance. Try to merge them all, giving
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349 // priority to the latest ones.
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350 DomainValue *dv = nullptr;
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351 while (!Regs.empty()) {
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352 if (!dv) {
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353 dv = LiveRegs[Regs.pop_back_val()];
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354 // Force the first dv to match the current instruction.
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355 dv->AvailableDomains = dv->getCommonDomains(available);
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356 assert(dv->AvailableDomains && "Domain should have been filtered");
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357 continue;
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358 }
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359
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360 DomainValue *Latest = LiveRegs[Regs.pop_back_val()];
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361 // Skip already merged values.
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362 if (Latest == dv || Latest->Next)
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363 continue;
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364 if (merge(dv, Latest))
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365 continue;
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366
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367 // If latest didn't merge, it is useless now. Kill all registers using it.
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368 for (int i : used) {
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369 assert(!LiveRegs.empty() && "no space allocated for live registers");
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370 if (LiveRegs[i] == Latest)
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371 kill(i);
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372 }
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373 }
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374
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375 // dv is the DomainValue we are going to use for this instruction.
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376 if (!dv) {
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377 dv = alloc();
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378 dv->AvailableDomains = available;
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379 }
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380 dv->Instrs.push_back(mi);
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381
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382 // Finally set all defs and non-collapsed uses to dv. We must iterate through
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383 // all the operators, including imp-def ones.
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384 for (MachineOperand &mo : mi->operands()) {
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385 if (!mo.isReg())
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386 continue;
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387 for (int rx : regIndices(mo.getReg())) {
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388 if (!LiveRegs[rx] || (mo.isDef() && LiveRegs[rx] != dv)) {
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389 kill(rx);
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390 setLiveReg(rx, dv);
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391 }
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392 }
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393 }
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394 }
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395
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396 void ExecutionDomainFix::processBasicBlock(
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397 const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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398 enterBasicBlock(TraversedMBB);
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399 // If this block is not done, it makes little sense to make any decisions
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400 // based on clearance information. We need to make a second pass anyway,
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401 // and by then we'll have better information, so we can avoid doing the work
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402 // to try and break dependencies now.
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403 for (MachineInstr &MI : *TraversedMBB.MBB) {
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404 if (!MI.isDebugValue()) {
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405 bool Kill = false;
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406 if (TraversedMBB.PrimaryPass)
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407 Kill = visitInstr(&MI);
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408 processDefs(&MI, Kill);
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409 }
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410 }
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411 leaveBasicBlock(TraversedMBB);
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412 }
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413
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414 bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
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415 if (skipFunction(mf.getFunction()))
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416 return false;
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417 MF = &mf;
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418 TII = MF->getSubtarget().getInstrInfo();
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419 TRI = MF->getSubtarget().getRegisterInfo();
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420 LiveRegs.clear();
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421 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
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422
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423 DEBUG(dbgs() << "********** FIX EXECUTION DOMAIN: "
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424 << TRI->getRegClassName(RC) << " **********\n");
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425
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426 // If no relevant registers are used in the function, we can skip it
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427 // completely.
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428 bool anyregs = false;
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429 const MachineRegisterInfo &MRI = mf.getRegInfo();
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430 for (unsigned Reg : *RC) {
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431 if (MRI.isPhysRegUsed(Reg)) {
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432 anyregs = true;
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433 break;
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434 }
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435 }
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436 if (!anyregs)
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437 return false;
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438
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439 RDA = &getAnalysis<ReachingDefAnalysis>();
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440
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441 // Initialize the AliasMap on the first use.
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442 if (AliasMap.empty()) {
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443 // Given a PhysReg, AliasMap[PhysReg] returns a list of indices into RC and
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444 // therefore the LiveRegs array.
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445 AliasMap.resize(TRI->getNumRegs());
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446 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
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447 for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true); AI.isValid();
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448 ++AI)
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449 AliasMap[*AI].push_back(i);
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450 }
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451
|
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452 // Initialize the MBBOutRegsInfos
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453 MBBOutRegsInfos.resize(mf.getNumBlockIDs());
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454
|
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455 // Traverse the basic blocks.
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456 LoopTraversal Traversal;
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457 LoopTraversal::TraversalOrder TraversedMBBOrder = Traversal.traverse(mf);
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458 for (LoopTraversal::TraversedMBBInfo TraversedMBB : TraversedMBBOrder) {
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459 processBasicBlock(TraversedMBB);
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460 }
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461
|
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462 for (LiveRegsDVInfo OutLiveRegs : MBBOutRegsInfos) {
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|
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463 for (DomainValue *OutLiveReg : OutLiveRegs) {
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|
|
464 if (OutLiveReg)
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|
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465 release(OutLiveReg);
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|
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466 }
|
|
|
467 }
|
|
|
468 MBBOutRegsInfos.clear();
|
|
|
469 Avail.clear();
|
|
|
470 Allocator.DestroyAll();
|
|
|
471
|
|
|
472 return false;
|
|
|
473 }
|
