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1 //===-------------- MIRCanonicalizer.cpp - MIR Canonicalizer --------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // The purpose of this pass is to employ a canonical code transformation so
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11 // that code compiled with slightly different IR passes can be diffed more
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12 // effectively than otherwise. This is done by renaming vregs in a given
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13 // LiveRange in a canonical way. This pass also does a pseudo-scheduling to
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14 // move defs closer to their use inorder to reduce diffs caused by slightly
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15 // different schedules.
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16 //
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17 // Basic Usage:
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18 //
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19 // llc -o - -run-pass mir-canonicalizer example.mir
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20 //
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21 // Reorders instructions canonically.
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22 // Renames virtual register operands canonically.
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23 // Strips certain MIR artifacts (optionally).
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24 //
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25 //===----------------------------------------------------------------------===//
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26
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27 #include "llvm/ADT/PostOrderIterator.h"
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28 #include "llvm/ADT/STLExtras.h"
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29 #include "llvm/CodeGen/MachineFunctionPass.h"
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30 #include "llvm/CodeGen/MachineInstrBuilder.h"
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31 #include "llvm/CodeGen/MachineRegisterInfo.h"
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32 #include "llvm/CodeGen/Passes.h"
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33 #include "llvm/Support/raw_ostream.h"
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34
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35 #include <queue>
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36
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37 using namespace llvm;
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38
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39 namespace llvm {
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40 extern char &MIRCanonicalizerID;
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41 } // namespace llvm
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42
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43 #define DEBUG_TYPE "mir-canonicalizer"
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44
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45 static cl::opt<unsigned>
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46 CanonicalizeFunctionNumber("canon-nth-function", cl::Hidden, cl::init(~0u),
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47 cl::value_desc("N"),
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48 cl::desc("Function number to canonicalize."));
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49
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50 static cl::opt<unsigned>
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51 CanonicalizeBasicBlockNumber("canon-nth-basicblock", cl::Hidden, cl::init(~0u),
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52 cl::value_desc("N"),
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53 cl::desc("BasicBlock number to canonicalize."));
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54
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55 namespace {
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56
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57 class MIRCanonicalizer : public MachineFunctionPass {
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58 public:
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59 static char ID;
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60 MIRCanonicalizer() : MachineFunctionPass(ID) {}
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61
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62 StringRef getPassName() const override {
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63 return "Rename register operands in a canonical ordering.";
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64 }
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65
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66 void getAnalysisUsage(AnalysisUsage &AU) const override {
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67 AU.setPreservesCFG();
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68 MachineFunctionPass::getAnalysisUsage(AU);
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69 }
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70
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71 bool runOnMachineFunction(MachineFunction &MF) override;
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72 };
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73
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74 } // end anonymous namespace
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75
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76 enum VRType { RSE_Reg = 0, RSE_FrameIndex, RSE_NewCandidate };
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77 class TypedVReg {
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78 VRType type;
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79 unsigned reg;
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80
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81 public:
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82 TypedVReg(unsigned reg) : type(RSE_Reg), reg(reg) {}
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83 TypedVReg(VRType type) : type(type), reg(~0U) {
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84 assert(type != RSE_Reg && "Expected a non-register type.");
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85 }
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86
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87 bool isReg() const { return type == RSE_Reg; }
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88 bool isFrameIndex() const { return type == RSE_FrameIndex; }
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89 bool isCandidate() const { return type == RSE_NewCandidate; }
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90
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91 VRType getType() const { return type; }
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92 unsigned getReg() const {
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93 assert(this->isReg() && "Expected a virtual or physical register.");
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94 return reg;
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95 }
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96 };
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97
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98 char MIRCanonicalizer::ID;
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99
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100 char &llvm::MIRCanonicalizerID = MIRCanonicalizer::ID;
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101
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102 INITIALIZE_PASS_BEGIN(MIRCanonicalizer, "mir-canonicalizer",
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103 "Rename Register Operands Canonically", false, false)
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104
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105 INITIALIZE_PASS_END(MIRCanonicalizer, "mir-canonicalizer",
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106 "Rename Register Operands Canonically", false, false)
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107
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108 static std::vector<MachineBasicBlock *> GetRPOList(MachineFunction &MF) {
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109 ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
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110 std::vector<MachineBasicBlock *> RPOList;
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111 for (auto MBB : RPOT) {
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112 RPOList.push_back(MBB);
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113 }
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114
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115 return RPOList;
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116 }
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117
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118 // Set a dummy vreg. We use this vregs register class to generate throw-away
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119 // vregs that are used to skip vreg numbers so that vreg numbers line up.
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120 static unsigned GetDummyVReg(const MachineFunction &MF) {
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121 for (auto &MBB : MF) {
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122 for (auto &MI : MBB) {
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123 for (auto &MO : MI.operands()) {
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124 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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125 continue;
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126 return MO.getReg();
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127 }
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128 }
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129 }
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130
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131 return ~0U;
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132 }
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133
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134 static bool rescheduleCanonically(MachineBasicBlock *MBB) {
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135
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136 bool Changed = false;
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137
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138 // Calculates the distance of MI from the begining of its parent BB.
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139 auto getInstrIdx = [](const MachineInstr &MI) {
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140 unsigned i = 0;
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141 for (auto &CurMI : *MI.getParent()) {
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142 if (&CurMI == &MI)
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143 return i;
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144 i++;
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145 }
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146 return ~0U;
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147 };
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148
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149 // Pre-Populate vector of instructions to reschedule so that we don't
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150 // clobber the iterator.
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151 std::vector<MachineInstr *> Instructions;
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152 for (auto &MI : *MBB) {
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153 Instructions.push_back(&MI);
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154 }
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155
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156 for (auto *II : Instructions) {
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157 if (II->getNumOperands() == 0)
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158 continue;
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159
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160 MachineOperand &MO = II->getOperand(0);
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161 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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162 continue;
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163
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164 DEBUG(dbgs() << "Operand " << 0 << " of "; II->dump(); MO.dump(););
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165
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166 MachineInstr *Def = II;
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167 unsigned Distance = ~0U;
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168 MachineInstr *UseToBringDefCloserTo = nullptr;
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169 MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
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170 for (auto &UO : MRI->use_nodbg_operands(MO.getReg())) {
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171 MachineInstr *UseInst = UO.getParent();
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172
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173 const unsigned DefLoc = getInstrIdx(*Def);
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174 const unsigned UseLoc = getInstrIdx(*UseInst);
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175 const unsigned Delta = (UseLoc - DefLoc);
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176
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177 if (UseInst->getParent() != Def->getParent())
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178 continue;
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179 if (DefLoc >= UseLoc)
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180 continue;
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181
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182 if (Delta < Distance) {
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183 Distance = Delta;
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184 UseToBringDefCloserTo = UseInst;
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185 }
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186 }
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187
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188 const auto BBE = MBB->instr_end();
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189 MachineBasicBlock::iterator DefI = BBE;
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190 MachineBasicBlock::iterator UseI = BBE;
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191
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192 for (auto BBI = MBB->instr_begin(); BBI != BBE; ++BBI) {
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193
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194 if (DefI != BBE && UseI != BBE)
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195 break;
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196
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197 if ((&*BBI != Def) && (&*BBI != UseToBringDefCloserTo))
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198 continue;
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199
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200 if (&*BBI == Def) {
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201 DefI = BBI;
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202 continue;
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203 }
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204
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205 if (&*BBI == UseToBringDefCloserTo) {
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206 UseI = BBI;
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207 continue;
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208 }
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209 }
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210
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211 if (DefI == BBE || UseI == BBE)
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212 continue;
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213
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214 DEBUG({
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215 dbgs() << "Splicing ";
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216 DefI->dump();
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217 dbgs() << " right before: ";
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218 UseI->dump();
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219 });
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220
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221 Changed = true;
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222 MBB->splice(UseI, MBB, DefI);
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223 }
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224
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225 return Changed;
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226 }
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227
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228 /// Here we find our candidates. What makes an interesting candidate?
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229 /// An candidate for a canonicalization tree root is normally any kind of
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230 /// instruction that causes side effects such as a store to memory or a copy to
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231 /// a physical register or a return instruction. We use these as an expression
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232 /// tree root that we walk inorder to build a canonical walk which should result
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233 /// in canoncal vreg renaming.
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234 static std::vector<MachineInstr *> populateCandidates(MachineBasicBlock *MBB) {
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235 std::vector<MachineInstr *> Candidates;
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236 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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237
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238 for (auto II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
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239 MachineInstr *MI = &*II;
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240
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241 bool DoesMISideEffect = false;
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242
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243 if (MI->getNumOperands() > 0 && MI->getOperand(0).isReg()) {
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244 const unsigned Dst = MI->getOperand(0).getReg();
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245 DoesMISideEffect |= !TargetRegisterInfo::isVirtualRegister(Dst);
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246
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247 for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI) {
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248 if (DoesMISideEffect) break;
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249 DoesMISideEffect |= (UI->getParent()->getParent() != MI->getParent());
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250 }
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251 }
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252
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253 if (!MI->mayStore() && !MI->isBranch() && !DoesMISideEffect)
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254 continue;
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255
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256 DEBUG(dbgs() << "Found Candidate: "; MI->dump(););
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257 Candidates.push_back(MI);
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258 }
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259
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260 return Candidates;
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261 }
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262
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263 static void doCandidateWalk(std::vector<TypedVReg> &VRegs,
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264 std::queue<TypedVReg> &RegQueue,
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265 std::vector<MachineInstr *> &VisitedMIs,
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266 const MachineBasicBlock *MBB) {
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267
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268 const MachineFunction &MF = *MBB->getParent();
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269 const MachineRegisterInfo &MRI = MF.getRegInfo();
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270
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271 while (!RegQueue.empty()) {
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272
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273 auto TReg = RegQueue.front();
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274 RegQueue.pop();
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275
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276 if (TReg.isFrameIndex()) {
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277 DEBUG(dbgs() << "Popping frame index.\n";);
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278 VRegs.push_back(TypedVReg(RSE_FrameIndex));
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279 continue;
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280 }
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281
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282 assert(TReg.isReg() && "Expected vreg or physreg.");
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283 unsigned Reg = TReg.getReg();
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284
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285 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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286 DEBUG({
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287 dbgs() << "Popping vreg ";
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288 MRI.def_begin(Reg)->dump();
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289 dbgs() << "\n";
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290 });
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291
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292 if (!llvm::any_of(VRegs, [&](const TypedVReg &TR) {
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293 return TR.isReg() && TR.getReg() == Reg;
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294 })) {
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295 VRegs.push_back(TypedVReg(Reg));
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296 }
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297 } else {
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298 DEBUG(dbgs() << "Popping physreg.\n";);
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299 VRegs.push_back(TypedVReg(Reg));
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300 continue;
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301 }
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302
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303 for (auto RI = MRI.def_begin(Reg), RE = MRI.def_end(); RI != RE; ++RI) {
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304 MachineInstr *Def = RI->getParent();
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305
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306 if (Def->getParent() != MBB)
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307 continue;
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308
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309 if (llvm::any_of(VisitedMIs,
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310 [&](const MachineInstr *VMI) { return Def == VMI; })) {
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311 break;
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312 }
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313
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314 DEBUG({
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315 dbgs() << "\n========================\n";
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316 dbgs() << "Visited MI: ";
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317 Def->dump();
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318 dbgs() << "BB Name: " << Def->getParent()->getName() << "\n";
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319 dbgs() << "\n========================\n";
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320 });
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321 VisitedMIs.push_back(Def);
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322 for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
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323
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324 MachineOperand &MO = Def->getOperand(I);
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325 if (MO.isFI()) {
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326 DEBUG(dbgs() << "Pushing frame index.\n";);
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327 RegQueue.push(TypedVReg(RSE_FrameIndex));
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328 }
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329
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330 if (!MO.isReg())
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331 continue;
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332 RegQueue.push(TypedVReg(MO.getReg()));
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333 }
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334 }
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335 }
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336 }
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337
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338 // TODO: Work to remove this in the future. One day when we have named vregs
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339 // we should be able to form the canonical name based on some characteristic
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340 // we see in that point of the expression tree (like if we were to name based
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341 // on some sort of value numbering scheme).
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342 static void SkipVRegs(unsigned &VRegGapIndex, MachineRegisterInfo &MRI,
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343 const TargetRegisterClass *RC) {
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344 const unsigned VR_GAP = (++VRegGapIndex * 1000);
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345
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346 DEBUG({
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347 dbgs() << "Adjusting per-BB VR_GAP for BB" << VRegGapIndex << " to "
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348 << VR_GAP << "\n";
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349 });
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350
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351 unsigned I = MRI.createVirtualRegister(RC);
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352 const unsigned E = (((I + VR_GAP) / VR_GAP) + 1) * VR_GAP;
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353 while (I != E) {
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354 I = MRI.createVirtualRegister(RC);
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355 }
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356 }
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357
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358 static std::map<unsigned, unsigned>
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359 GetVRegRenameMap(const std::vector<TypedVReg> &VRegs,
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360 const std::vector<unsigned> &renamedInOtherBB,
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361 MachineRegisterInfo &MRI,
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362 const TargetRegisterClass *RC) {
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363 std::map<unsigned, unsigned> VRegRenameMap;
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364 unsigned LastRenameReg = MRI.createVirtualRegister(RC);
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365 bool FirstCandidate = true;
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366
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367 for (auto &vreg : VRegs) {
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368 if (vreg.isFrameIndex()) {
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369 // We skip one vreg for any frame index because there is a good chance
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370 // (especially when comparing SelectionDAG to GlobalISel generated MIR)
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371 // that in the other file we are just getting an incoming vreg that comes
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372 // from a copy from a frame index. So it's safe to skip by one.
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373 LastRenameReg = MRI.createVirtualRegister(RC);
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374 DEBUG(dbgs() << "Skipping rename for FI " << LastRenameReg << "\n";);
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375 continue;
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376 } else if (vreg.isCandidate()) {
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377
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378 // After the first candidate, for every subsequent candidate, we skip mod
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379 // 10 registers so that the candidates are more likely to start at the
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380 // same vreg number making it more likely that the canonical walk from the
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381 // candidate insruction. We don't need to skip from the first candidate of
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382 // the BasicBlock because we already skip ahead several vregs for each BB.
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383 while (LastRenameReg % 10) {
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384 if (!FirstCandidate) break;
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385 LastRenameReg = MRI.createVirtualRegister(RC);
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386
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387 DEBUG({
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388 dbgs() << "Skipping rename for new candidate " << LastRenameReg
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389 << "\n";
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390 });
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391 }
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392 FirstCandidate = false;
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393 continue;
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394 } else if (!TargetRegisterInfo::isVirtualRegister(vreg.getReg())) {
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395 LastRenameReg = MRI.createVirtualRegister(RC);
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396 DEBUG({
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397 dbgs() << "Skipping rename for Phys Reg " << LastRenameReg << "\n";
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398 });
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399 continue;
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400 }
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401
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402 auto Reg = vreg.getReg();
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403 if (llvm::find(renamedInOtherBB, Reg) != renamedInOtherBB.end()) {
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404 DEBUG(dbgs() << "Vreg " << Reg << " already renamed in other BB.\n";);
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405 continue;
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406 }
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407
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408 auto Rename = MRI.createVirtualRegister(MRI.getRegClass(Reg));
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409 LastRenameReg = Rename;
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410
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411 if (VRegRenameMap.find(Reg) == VRegRenameMap.end()) {
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412 DEBUG(dbgs() << "Mapping vreg ";);
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413 if (MRI.reg_begin(Reg) != MRI.reg_end()) {
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414 DEBUG(auto foo = &*MRI.reg_begin(Reg); foo->dump(););
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415 } else {
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416 DEBUG(dbgs() << Reg;);
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417 }
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418 DEBUG(dbgs() << " to ";);
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419 if (MRI.reg_begin(Rename) != MRI.reg_end()) {
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420 DEBUG(auto foo = &*MRI.reg_begin(Rename); foo->dump(););
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421 } else {
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422 DEBUG(dbgs() << Rename;);
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423 }
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424 DEBUG(dbgs() << "\n";);
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425
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426 VRegRenameMap.insert(std::pair<unsigned, unsigned>(Reg, Rename));
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427 }
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428 }
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429
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430 return VRegRenameMap;
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431 }
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432
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433 static bool doVRegRenaming(std::vector<unsigned> &RenamedInOtherBB,
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434 const std::map<unsigned, unsigned> &VRegRenameMap,
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435 MachineRegisterInfo &MRI) {
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436 bool Changed = false;
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437 for (auto I = VRegRenameMap.begin(), E = VRegRenameMap.end(); I != E; ++I) {
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438
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439 auto VReg = I->first;
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440 auto Rename = I->second;
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441
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442 RenamedInOtherBB.push_back(Rename);
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443
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444 std::vector<MachineOperand *> RenameMOs;
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445 for (auto &MO : MRI.reg_operands(VReg)) {
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446 RenameMOs.push_back(&MO);
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447 }
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448
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449 for (auto *MO : RenameMOs) {
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450 Changed = true;
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451 MO->setReg(Rename);
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452
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453 if (!MO->isDef())
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454 MO->setIsKill(false);
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455 }
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456 }
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457
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458 return Changed;
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459 }
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460
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461 static bool doDefKillClear(MachineBasicBlock *MBB) {
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462 bool Changed = false;
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463
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464 for (auto &MI : *MBB) {
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465 for (auto &MO : MI.operands()) {
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466 if (!MO.isReg())
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467 continue;
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468 if (!MO.isDef() && MO.isKill()) {
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469 Changed = true;
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470 MO.setIsKill(false);
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471 }
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472
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473 if (MO.isDef() && MO.isDead()) {
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474 Changed = true;
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475 MO.setIsDead(false);
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476 }
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477 }
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478 }
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479
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480 return Changed;
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481 }
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482
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483 static bool runOnBasicBlock(MachineBasicBlock *MBB,
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484 std::vector<StringRef> &bbNames,
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485 std::vector<unsigned> &renamedInOtherBB,
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486 unsigned &basicBlockNum, unsigned &VRegGapIndex) {
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487
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488 if (CanonicalizeBasicBlockNumber != ~0U) {
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489 if (CanonicalizeBasicBlockNumber != basicBlockNum++)
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490 return false;
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491 DEBUG(dbgs() << "\n Canonicalizing BasicBlock " << MBB->getName() << "\n";);
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492 }
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493
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494 if (llvm::find(bbNames, MBB->getName()) != bbNames.end()) {
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495 DEBUG({
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496 dbgs() << "Found potentially duplicate BasicBlocks: " << MBB->getName()
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497 << "\n";
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498 });
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499 return false;
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500 }
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501
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502 DEBUG({
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503 dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << " \n\n";
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504 dbgs() << "\n\n================================================\n\n";
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505 });
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506
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507 bool Changed = false;
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508 MachineFunction &MF = *MBB->getParent();
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|
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509 MachineRegisterInfo &MRI = MF.getRegInfo();
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|
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510
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|
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511 const unsigned DummyVReg = GetDummyVReg(MF);
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|
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512 const TargetRegisterClass *DummyRC =
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|
|
513 (DummyVReg == ~0U) ? nullptr : MRI.getRegClass(DummyVReg);
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|
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514 if (!DummyRC) return false;
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|
|
515
|
|
|
516 bbNames.push_back(MBB->getName());
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|
|
517 DEBUG(dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << "\n\n";);
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|
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518
|
|
|
519 DEBUG(dbgs() << "MBB Before Scheduling:\n"; MBB->dump(););
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|
|
520 Changed |= rescheduleCanonically(MBB);
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|
|
521 DEBUG(dbgs() << "MBB After Scheduling:\n"; MBB->dump(););
|
|
|
522
|
|
|
523 std::vector<MachineInstr *> Candidates = populateCandidates(MBB);
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|
|
524 std::vector<MachineInstr *> VisitedMIs;
|
|
|
525 std::copy(Candidates.begin(), Candidates.end(),
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|
|
526 std::back_inserter(VisitedMIs));
|
|
|
527
|
|
|
528 std::vector<TypedVReg> VRegs;
|
|
|
529 for (auto candidate : Candidates) {
|
|
|
530 VRegs.push_back(TypedVReg(RSE_NewCandidate));
|
|
|
531
|
|
|
532 std::queue<TypedVReg> RegQueue;
|
|
|
533
|
|
|
534 // Here we walk the vreg operands of a non-root node along our walk.
|
|
|
535 // The root nodes are the original candidates (stores normally).
|
|
|
536 // These are normally not the root nodes (except for the case of copies to
|
|
|
537 // physical registers).
|
|
|
538 for (unsigned i = 1; i < candidate->getNumOperands(); i++) {
|
|
|
539 if (candidate->mayStore() || candidate->isBranch())
|
|
|
540 break;
|
|
|
541
|
|
|
542 MachineOperand &MO = candidate->getOperand(i);
|
|
|
543 if (!(MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())))
|
|
|
544 continue;
|
|
|
545
|
|
|
546 DEBUG(dbgs() << "Enqueue register"; MO.dump(); dbgs() << "\n";);
|
|
|
547 RegQueue.push(TypedVReg(MO.getReg()));
|
|
|
548 }
|
|
|
549
|
|
|
550 // Here we walk the root candidates. We start from the 0th operand because
|
|
|
551 // the root is normally a store to a vreg.
|
|
|
552 for (unsigned i = 0; i < candidate->getNumOperands(); i++) {
|
|
|
553
|
|
|
554 if (!candidate->mayStore() && !candidate->isBranch())
|
|
|
555 break;
|
|
|
556
|
|
|
557 MachineOperand &MO = candidate->getOperand(i);
|
|
|
558
|
|
|
559 // TODO: Do we want to only add vregs here?
|
|
|
560 if (!MO.isReg() && !MO.isFI())
|
|
|
561 continue;
|
|
|
562
|
|
|
563 DEBUG(dbgs() << "Enqueue Reg/FI"; MO.dump(); dbgs() << "\n";);
|
|
|
564
|
|
|
565 RegQueue.push(MO.isReg() ? TypedVReg(MO.getReg()) :
|
|
|
566 TypedVReg(RSE_FrameIndex));
|
|
|
567 }
|
|
|
568
|
|
|
569 doCandidateWalk(VRegs, RegQueue, VisitedMIs, MBB);
|
|
|
570 }
|
|
|
571
|
|
|
572 // If we have populated no vregs to rename then bail.
|
|
|
573 // The rest of this function does the vreg remaping.
|
|
|
574 if (VRegs.size() == 0)
|
|
|
575 return Changed;
|
|
|
576
|
|
|
577 // Skip some vregs, so we can recon where we'll land next.
|
|
|
578 SkipVRegs(VRegGapIndex, MRI, DummyRC);
|
|
|
579
|
|
|
580 auto VRegRenameMap = GetVRegRenameMap(VRegs, renamedInOtherBB, MRI, DummyRC);
|
|
|
581 Changed |= doVRegRenaming(renamedInOtherBB, VRegRenameMap, MRI);
|
|
|
582 Changed |= doDefKillClear(MBB);
|
|
|
583
|
|
|
584 DEBUG(dbgs() << "Updated MachineBasicBlock:\n"; MBB->dump(); dbgs() << "\n";);
|
|
|
585 DEBUG(dbgs() << "\n\n================================================\n\n");
|
|
|
586 return Changed;
|
|
|
587 }
|
|
|
588
|
|
|
589 bool MIRCanonicalizer::runOnMachineFunction(MachineFunction &MF) {
|
|
|
590
|
|
|
591 static unsigned functionNum = 0;
|
|
|
592 if (CanonicalizeFunctionNumber != ~0U) {
|
|
|
593 if (CanonicalizeFunctionNumber != functionNum++)
|
|
|
594 return false;
|
|
|
595 DEBUG(dbgs() << "\n Canonicalizing Function " << MF.getName() << "\n";);
|
|
|
596 }
|
|
|
597
|
|
|
598 // we need a valid vreg to create a vreg type for skipping all those
|
|
|
599 // stray vreg numbers so reach alignment/canonical vreg values.
|
|
|
600 std::vector<MachineBasicBlock*> RPOList = GetRPOList(MF);
|
|
|
601
|
|
|
602 DEBUG(
|
|
|
603 dbgs() << "\n\n NEW MACHINE FUNCTION: " << MF.getName() << " \n\n";
|
|
|
604 dbgs() << "\n\n================================================\n\n";
|
|
|
605 dbgs() << "Total Basic Blocks: " << RPOList.size() << "\n";
|
|
|
606 for (auto MBB : RPOList) {
|
|
|
607 dbgs() << MBB->getName() << "\n";
|
|
|
608 }
|
|
|
609 dbgs() << "\n\n================================================\n\n";
|
|
|
610 );
|
|
|
611
|
|
|
612 std::vector<StringRef> BBNames;
|
|
|
613 std::vector<unsigned> RenamedInOtherBB;
|
|
|
614
|
|
|
615 unsigned GapIdx = 0;
|
|
|
616 unsigned BBNum = 0;
|
|
|
617
|
|
|
618 bool Changed = false;
|
|
|
619
|
|
|
620 for (auto MBB : RPOList)
|
|
|
621 Changed |= runOnBasicBlock(MBB, BBNames, RenamedInOtherBB, BBNum, GapIdx);
|
|
|
622
|
|
|
623 return Changed;
|
|
|
624 }
|
|
|
625
|
