annotate lib/CodeGen/MachineCopyPropagation.cpp @ 134:3a76565eade5 LLVM5.0.1

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1 //===- MachineCopyPropagation.cpp - Machine Copy Propagation Pass ---------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This is an extremely simple MachineInstr-level copy propagation pass.
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11 //
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12 // This pass forwards the source of COPYs to the users of their destinations
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13 // when doing so is legal. For example:
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14 //
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15 // %reg1 = COPY %reg0
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16 // ...
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17 // ... = OP %reg1
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18 //
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19 // If
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20 // - %reg0 has not been clobbered by the time of the use of %reg1
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21 // - the register class constraints are satisfied
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22 // - the COPY def is the only value that reaches OP
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23 // then this pass replaces the above with:
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24 //
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25 // %reg1 = COPY %reg0
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26 // ...
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27 // ... = OP %reg0
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28 //
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29 // This pass also removes some redundant COPYs. For example:
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30 //
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31 // %R1 = COPY %R0
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32 // ... // No clobber of %R1
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33 // %R0 = COPY %R1 <<< Removed
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34 //
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35 // or
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36 //
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37 // %R1 = COPY %R0
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38 // ... // No clobber of %R0
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39 // %R1 = COPY %R0 <<< Removed
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40 //
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41 //===----------------------------------------------------------------------===//
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42
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43 #include "llvm/ADT/DenseMap.h"
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44 #include "llvm/ADT/STLExtras.h"
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45 #include "llvm/ADT/SetVector.h"
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46 #include "llvm/ADT/SmallVector.h"
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47 #include "llvm/ADT/Statistic.h"
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48 #include "llvm/ADT/iterator_range.h"
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49 #include "llvm/CodeGen/MachineBasicBlock.h"
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50 #include "llvm/CodeGen/MachineFunction.h"
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51 #include "llvm/CodeGen/MachineFunctionPass.h"
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52 #include "llvm/CodeGen/MachineInstr.h"
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53 #include "llvm/CodeGen/MachineOperand.h"
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54 #include "llvm/CodeGen/MachineRegisterInfo.h"
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55 #include "llvm/CodeGen/TargetInstrInfo.h"
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56 #include "llvm/CodeGen/TargetRegisterInfo.h"
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57 #include "llvm/CodeGen/TargetSubtargetInfo.h"
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58 #include "llvm/MC/MCRegisterInfo.h"
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59 #include "llvm/Pass.h"
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60 #include "llvm/Support/Debug.h"
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61 #include "llvm/Support/DebugCounter.h"
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62 #include "llvm/Support/raw_ostream.h"
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63 #include <cassert>
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64 #include <iterator>
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65
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66 using namespace llvm;
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67
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68 #define DEBUG_TYPE "machine-cp"
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69
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70 STATISTIC(NumDeletes, "Number of dead copies deleted");
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71 STATISTIC(NumCopyForwards, "Number of copy uses forwarded");
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72 DEBUG_COUNTER(FwdCounter, "machine-cp-fwd",
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73 "Controls which register COPYs are forwarded");
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74
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75 namespace {
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76
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77 using RegList = SmallVector<unsigned, 4>;
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78 using SourceMap = DenseMap<unsigned, RegList>;
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79 using Reg2MIMap = DenseMap<unsigned, MachineInstr *>;
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80
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81 class MachineCopyPropagation : public MachineFunctionPass {
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82 const TargetRegisterInfo *TRI;
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83 const TargetInstrInfo *TII;
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84 const MachineRegisterInfo *MRI;
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85
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86 public:
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87 static char ID; // Pass identification, replacement for typeid
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88
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89 MachineCopyPropagation() : MachineFunctionPass(ID) {
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90 initializeMachineCopyPropagationPass(*PassRegistry::getPassRegistry());
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91 }
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92
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93 void getAnalysisUsage(AnalysisUsage &AU) const override {
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94 AU.setPreservesCFG();
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95 MachineFunctionPass::getAnalysisUsage(AU);
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96 }
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97
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98 bool runOnMachineFunction(MachineFunction &MF) override;
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99
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100 MachineFunctionProperties getRequiredProperties() const override {
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101 return MachineFunctionProperties().set(
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102 MachineFunctionProperties::Property::NoVRegs);
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103 }
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104
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105 private:
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106 void ClobberRegister(unsigned Reg);
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107 void ReadRegister(unsigned Reg);
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108 void CopyPropagateBlock(MachineBasicBlock &MBB);
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109 bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
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110 void forwardUses(MachineInstr &MI);
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111 bool isForwardableRegClassCopy(const MachineInstr &Copy,
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112 const MachineInstr &UseI, unsigned UseIdx);
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113 bool hasImplicitOverlap(const MachineInstr &MI, const MachineOperand &Use);
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114
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115 /// Candidates for deletion.
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116 SmallSetVector<MachineInstr*, 8> MaybeDeadCopies;
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117
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118 /// Def -> available copies map.
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119 Reg2MIMap AvailCopyMap;
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120
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121 /// Def -> copies map.
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122 Reg2MIMap CopyMap;
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123
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124 /// Src -> Def map
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125 SourceMap SrcMap;
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126
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127 bool Changed;
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128 };
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129
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130 } // end anonymous namespace
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131
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132 char MachineCopyPropagation::ID = 0;
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133
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134 char &llvm::MachineCopyPropagationID = MachineCopyPropagation::ID;
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135
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136 INITIALIZE_PASS(MachineCopyPropagation, DEBUG_TYPE,
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137 "Machine Copy Propagation Pass", false, false)
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138
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139 /// Remove any entry in \p Map where the register is a subregister or equal to
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140 /// a register contained in \p Regs.
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141 static void removeRegsFromMap(Reg2MIMap &Map, const RegList &Regs,
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142 const TargetRegisterInfo &TRI) {
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143 for (unsigned Reg : Regs) {
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144 // Source of copy is no longer available for propagation.
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145 for (MCSubRegIterator SR(Reg, &TRI, true); SR.isValid(); ++SR)
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146 Map.erase(*SR);
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147 }
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148 }
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149
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150 /// Remove any entry in \p Map that is marked clobbered in \p RegMask.
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151 /// The map will typically have a lot fewer entries than the regmask clobbers,
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152 /// so this is more efficient than iterating the clobbered registers and calling
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153 /// ClobberRegister() on them.
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154 static void removeClobberedRegsFromMap(Reg2MIMap &Map,
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155 const MachineOperand &RegMask) {
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156 for (Reg2MIMap::iterator I = Map.begin(), E = Map.end(), Next; I != E;
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157 I = Next) {
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158 Next = std::next(I);
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159 unsigned Reg = I->first;
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160 if (RegMask.clobbersPhysReg(Reg))
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161 Map.erase(I);
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162 }
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163 }
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164
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165 void MachineCopyPropagation::ClobberRegister(unsigned Reg) {
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166 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
120
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diff changeset
167 CopyMap.erase(*AI);
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diff changeset
168 AvailCopyMap.erase(*AI);
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diff changeset
169
0
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diff changeset
170 SourceMap::iterator SI = SrcMap.find(*AI);
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parents:
diff changeset
171 if (SI != SrcMap.end()) {
120
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diff changeset
172 removeRegsFromMap(AvailCopyMap, SI->second, *TRI);
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173 SrcMap.erase(SI);
0
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diff changeset
174 }
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parents:
diff changeset
175 }
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parents:
diff changeset
176 }
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parents:
diff changeset
177
121
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diff changeset
178 void MachineCopyPropagation::ReadRegister(unsigned Reg) {
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179 // If 'Reg' is defined by a copy, the copy is no longer a candidate
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180 // for elimination.
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diff changeset
181 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
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diff changeset
182 Reg2MIMap::iterator CI = CopyMap.find(*AI);
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diff changeset
183 if (CI != CopyMap.end()) {
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184 DEBUG(dbgs() << "MCP: Copy is used - not dead: "; CI->second->dump());
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diff changeset
185 MaybeDeadCopies.remove(CI->second);
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186 }
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diff changeset
187 }
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188 }
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189
120
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190 /// Return true if \p PreviousCopy did copy register \p Src to register \p Def.
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191 /// This fact may have been obscured by sub register usage or may not be true at
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192 /// all even though Src and Def are subregisters of the registers used in
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193 /// PreviousCopy. e.g.
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194 /// isNopCopy("ecx = COPY eax", AX, CX) == true
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195 /// isNopCopy("ecx = COPY eax", AH, CL) == false
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196 static bool isNopCopy(const MachineInstr &PreviousCopy, unsigned Src,
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197 unsigned Def, const TargetRegisterInfo *TRI) {
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198 unsigned PreviousSrc = PreviousCopy.getOperand(1).getReg();
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199 unsigned PreviousDef = PreviousCopy.getOperand(0).getReg();
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200 if (Src == PreviousSrc) {
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201 assert(Def == PreviousDef);
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202 return true;
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203 }
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204 if (!TRI->isSubRegister(PreviousSrc, Src))
0
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205 return false;
120
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206 unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src);
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207 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def);
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208 }
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209
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210 /// Remove instruction \p Copy if there exists a previous copy that copies the
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211 /// register \p Src to the register \p Def; This may happen indirectly by
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212 /// copying the super registers.
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213 bool MachineCopyPropagation::eraseIfRedundant(MachineInstr &Copy, unsigned Src,
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214 unsigned Def) {
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215 // Avoid eliminating a copy from/to a reserved registers as we cannot predict
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216 // the value (Example: The sparc zero register is writable but stays zero).
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217 if (MRI->isReserved(Src) || MRI->isReserved(Def))
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218 return false;
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219
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220 // Search for an existing copy.
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221 Reg2MIMap::iterator CI = AvailCopyMap.find(Def);
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222 if (CI == AvailCopyMap.end())
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223 return false;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
224
120
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diff changeset
225 // Check that the existing copy uses the correct sub registers.
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226 MachineInstr &PrevCopy = *CI->second;
134
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diff changeset
227 if (PrevCopy.getOperand(0).isDead())
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diff changeset
228 return false;
120
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diff changeset
229 if (!isNopCopy(PrevCopy, Src, Def, TRI))
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diff changeset
230 return false;
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diff changeset
231
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232 DEBUG(dbgs() << "MCP: copy is a NOP, removing: "; Copy.dump());
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233
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234 // Copy was redundantly redefining either Src or Def. Remove earlier kill
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diff changeset
235 // flags between Copy and PrevCopy because the value will be reused now.
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diff changeset
236 assert(Copy.isCopy());
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diff changeset
237 unsigned CopyDef = Copy.getOperand(0).getReg();
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238 assert(CopyDef == Src || CopyDef == Def);
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239 for (MachineInstr &MI :
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diff changeset
240 make_range(PrevCopy.getIterator(), Copy.getIterator()))
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diff changeset
241 MI.clearRegisterKills(CopyDef, TRI);
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242
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diff changeset
243 Copy.eraseFromParent();
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diff changeset
244 Changed = true;
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diff changeset
245 ++NumDeletes;
0
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parents:
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246 return true;
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parents:
diff changeset
247 }
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parents:
diff changeset
248
134
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249 /// Decide whether we should forward the source of \param Copy to its use in
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250 /// \param UseI based on the physical register class constraints of the opcode
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251 /// and avoiding introducing more cross-class COPYs.
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diff changeset
252 bool MachineCopyPropagation::isForwardableRegClassCopy(const MachineInstr &Copy,
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diff changeset
253 const MachineInstr &UseI,
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parents: 121
diff changeset
254 unsigned UseIdx) {
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parents: 121
diff changeset
255
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diff changeset
256 unsigned CopySrcReg = Copy.getOperand(1).getReg();
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diff changeset
257
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diff changeset
258 // If the new register meets the opcode register constraints, then allow
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259 // forwarding.
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diff changeset
260 if (const TargetRegisterClass *URC =
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diff changeset
261 UseI.getRegClassConstraint(UseIdx, TII, TRI))
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
262 return URC->contains(CopySrcReg);
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diff changeset
263
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
264 if (!UseI.isCopy())
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parents: 121
diff changeset
265 return false;
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diff changeset
266
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diff changeset
267 /// COPYs don't have register class constraints, so if the user instruction
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diff changeset
268 /// is a COPY, we just try to avoid introducing additional cross-class
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diff changeset
269 /// COPYs. For example:
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parents: 121
diff changeset
270 ///
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parents: 121
diff changeset
271 /// RegClassA = COPY RegClassB // Copy parameter
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parents: 121
diff changeset
272 /// ...
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parents: 121
diff changeset
273 /// RegClassB = COPY RegClassA // UseI parameter
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parents: 121
diff changeset
274 ///
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parents: 121
diff changeset
275 /// which after forwarding becomes
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mir3636
parents: 121
diff changeset
276 ///
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parents: 121
diff changeset
277 /// RegClassA = COPY RegClassB
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
278 /// ...
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diff changeset
279 /// RegClassB = COPY RegClassB
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
280 ///
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parents: 121
diff changeset
281 /// so we have reduced the number of cross-class COPYs and potentially
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
282 /// introduced a nop COPY that can be removed.
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
283 const TargetRegisterClass *UseDstRC =
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
284 TRI->getMinimalPhysRegClass(UseI.getOperand(0).getReg());
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
285
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
286 const TargetRegisterClass *SuperRC = UseDstRC;
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
287 for (TargetRegisterClass::sc_iterator SuperRCI = UseDstRC->getSuperClasses();
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
288 SuperRC; SuperRC = *SuperRCI++)
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
289 if (SuperRC->contains(CopySrcReg))
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
290 return true;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
291
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
292 return false;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
293 }
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
294
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
295 /// Check that \p MI does not have implicit uses that overlap with it's \p Use
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
296 /// operand (the register being replaced), since these can sometimes be
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
297 /// implicitly tied to other operands. For example, on AMDGPU:
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
298 ///
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
299 /// V_MOVRELS_B32_e32 %VGPR2, %M0<imp-use>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use>
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
300 ///
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
301 /// the %VGPR2 is implicitly tied to the larger reg operand, but we have no
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
302 /// way of knowing we need to update the latter when updating the former.
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
303 bool MachineCopyPropagation::hasImplicitOverlap(const MachineInstr &MI,
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
304 const MachineOperand &Use) {
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
305 for (const MachineOperand &MIUse : MI.uses())
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
306 if (&MIUse != &Use && MIUse.isReg() && MIUse.isImplicit() &&
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
307 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg()))
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
308 return true;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
309
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
310 return false;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
311 }
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
312
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
313 /// Look for available copies whose destination register is used by \p MI and
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
314 /// replace the use in \p MI with the copy's source register.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
315 void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
316 if (AvailCopyMap.empty())
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
317 return;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
318
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
319 // Look for non-tied explicit vreg uses that have an active COPY
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
320 // instruction that defines the physical register allocated to them.
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mir3636
parents: 121
diff changeset
321 // Replace the vreg with the source of the active COPY.
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parents: 121
diff changeset
322 for (unsigned OpIdx = 0, OpEnd = MI.getNumOperands(); OpIdx < OpEnd;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
323 ++OpIdx) {
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
324 MachineOperand &MOUse = MI.getOperand(OpIdx);
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
325 // Don't forward into undef use operands since doing so can cause problems
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parents: 121
diff changeset
326 // with the machine verifier, since it doesn't treat undef reads as reads,
3a76565eade5 update 5.0.1
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parents: 121
diff changeset
327 // so we can end up with a live range that ends on an undef read, leading to
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
328 // an error that the live range doesn't end on a read of the live range
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
329 // register.
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mir3636
parents: 121
diff changeset
330 if (!MOUse.isReg() || MOUse.isTied() || MOUse.isUndef() || MOUse.isDef() ||
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
331 MOUse.isImplicit())
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
332 continue;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
333
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
334 if (!MOUse.getReg())
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
335 continue;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
336
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
337 // Check that the register is marked 'renamable' so we know it is safe to
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
338 // rename it without violating any constraints that aren't expressed in the
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
339 // IR (e.g. ABI or opcode requirements).
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
340 if (!MOUse.isRenamable())
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
341 continue;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
342
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
343 auto CI = AvailCopyMap.find(MOUse.getReg());
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
344 if (CI == AvailCopyMap.end())
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
345 continue;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
346
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
347 MachineInstr &Copy = *CI->second;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
348 unsigned CopyDstReg = Copy.getOperand(0).getReg();
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
349 const MachineOperand &CopySrc = Copy.getOperand(1);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
350 unsigned CopySrcReg = CopySrc.getReg();
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
351
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
352 // FIXME: Don't handle partial uses of wider COPYs yet.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
353 if (MOUse.getReg() != CopyDstReg) {
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
354 DEBUG(dbgs() << "MCP: FIXME! Not forwarding COPY to sub-register use:\n "
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
355 << MI);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
356 continue;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
357 }
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
358
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
359 // Don't forward COPYs of reserved regs unless they are constant.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
360 if (MRI->isReserved(CopySrcReg) && !MRI->isConstantPhysReg(CopySrcReg))
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
361 continue;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
362
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
363 if (!isForwardableRegClassCopy(Copy, MI, OpIdx))
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
364 continue;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
365
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
366 if (hasImplicitOverlap(MI, MOUse))
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
367 continue;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
368
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
369 if (!DebugCounter::shouldExecute(FwdCounter)) {
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
370 DEBUG(dbgs() << "MCP: Skipping forwarding due to debug counter:\n "
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
371 << MI);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
372 continue;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
373 }
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
374
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
375 DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI)
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
376 << "\n with " << printReg(CopySrcReg, TRI) << "\n in "
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
377 << MI << " from " << Copy);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
378
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
379 MOUse.setReg(CopySrcReg);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
380 if (!CopySrc.isRenamable())
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
381 MOUse.setIsRenamable(false);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
382
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
383 DEBUG(dbgs() << "MCP: After replacement: " << MI << "\n");
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
384
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
385 // Clear kill markers that may have been invalidated.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
386 for (MachineInstr &KMI :
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
387 make_range(Copy.getIterator(), std::next(MI.getIterator())))
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
388 KMI.clearRegisterKills(CopySrcReg, TRI);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
389
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
390 ++NumCopyForwards;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
391 Changed = true;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
392 }
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
393 }
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
394
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
395 void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
396 DEBUG(dbgs() << "MCP: CopyPropagateBlock " << MBB.getName() << "\n");
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
397
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
398 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
399 MachineInstr *MI = &*I;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
400 ++I;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
401
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
402 if (MI->isCopy()) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
403 unsigned Def = MI->getOperand(0).getReg();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
404 unsigned Src = MI->getOperand(1).getReg();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
405
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
406 assert(!TargetRegisterInfo::isVirtualRegister(Def) &&
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
407 !TargetRegisterInfo::isVirtualRegister(Src) &&
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
408 "MachineCopyPropagation should be run after register allocation!");
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
409
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
410 // The two copies cancel out and the source of the first copy
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
411 // hasn't been overridden, eliminate the second one. e.g.
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
412 // %ecx = COPY %eax
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
413 // ... nothing clobbered eax.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
414 // %eax = COPY %ecx
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
415 // =>
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
416 // %ecx = COPY %eax
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
417 //
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
418 // or
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
419 //
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
420 // %ecx = COPY %eax
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
421 // ... nothing clobbered eax.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
422 // %ecx = COPY %eax
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
423 // =>
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
424 // %ecx = COPY %eax
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
425 if (eraseIfRedundant(*MI, Def, Src) || eraseIfRedundant(*MI, Src, Def))
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
426 continue;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
427
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
428 forwardUses(*MI);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
429
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
430 // Src may have been changed by forwardUses()
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
431 Src = MI->getOperand(1).getReg();
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
432
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
433 // If Src is defined by a previous copy, the previous copy cannot be
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
434 // eliminated.
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
435 ReadRegister(Src);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
436 for (const MachineOperand &MO : MI->implicit_operands()) {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
437 if (!MO.isReg() || !MO.readsReg())
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
438 continue;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
439 unsigned Reg = MO.getReg();
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
440 if (!Reg)
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
441 continue;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
442 ReadRegister(Reg);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
443 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
444
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
445 DEBUG(dbgs() << "MCP: Copy is a deletion candidate: "; MI->dump());
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
446
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
447 // Copy is now a candidate for deletion.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
448 if (!MRI->isReserved(Def))
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
449 MaybeDeadCopies.insert(MI);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
450
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
451 // If 'Def' is previously source of another copy, then this earlier copy's
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
452 // source is no longer available. e.g.
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
453 // %xmm9 = copy %xmm2
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
454 // ...
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
455 // %xmm2 = copy %xmm0
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
456 // ...
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
457 // %xmm2 = copy %xmm9
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
458 ClobberRegister(Def);
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
459 for (const MachineOperand &MO : MI->implicit_operands()) {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
460 if (!MO.isReg() || !MO.isDef())
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
461 continue;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
462 unsigned Reg = MO.getReg();
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
463 if (!Reg)
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
464 continue;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
465 ClobberRegister(Reg);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
466 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
467
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
468 // Remember Def is defined by the copy.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
469 for (MCSubRegIterator SR(Def, TRI, /*IncludeSelf=*/true); SR.isValid();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
470 ++SR) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
471 CopyMap[*SR] = MI;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
472 AvailCopyMap[*SR] = MI;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
473 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
474
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
475 // Remember source that's copied to Def. Once it's clobbered, then
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
476 // it's no longer available for copy propagation.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
477 RegList &DestList = SrcMap[Src];
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
478 if (!is_contained(DestList, Def))
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
479 DestList.push_back(Def);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
480
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
481 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
482 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
483
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
484 // Clobber any earlyclobber regs first.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
485 for (const MachineOperand &MO : MI->operands())
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
486 if (MO.isReg() && MO.isEarlyClobber()) {
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
487 unsigned Reg = MO.getReg();
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
488 // If we have a tied earlyclobber, that means it is also read by this
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
489 // instruction, so we need to make sure we don't remove it as dead
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
490 // later.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
491 if (MO.isTied())
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
492 ReadRegister(Reg);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
493 ClobberRegister(Reg);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
494 }
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
495
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
496 forwardUses(*MI);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
497
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
498 // Not a copy.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
499 SmallVector<unsigned, 2> Defs;
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
500 const MachineOperand *RegMask = nullptr;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
501 for (const MachineOperand &MO : MI->operands()) {
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
502 if (MO.isRegMask())
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
503 RegMask = &MO;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
504 if (!MO.isReg())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
505 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
506 unsigned Reg = MO.getReg();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
507 if (!Reg)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
508 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
509
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
510 assert(!TargetRegisterInfo::isVirtualRegister(Reg) &&
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
511 "MachineCopyPropagation should be run after register allocation!");
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
512
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
513 if (MO.isDef() && !MO.isEarlyClobber()) {
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
514 Defs.push_back(Reg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
515 continue;
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
516 } else if (MO.readsReg())
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
517 ReadRegister(Reg);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
518 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
519
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
520 // The instruction has a register mask operand which means that it clobbers
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
521 // a large set of registers. Treat clobbered registers the same way as
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
522 // defined registers.
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
523 if (RegMask) {
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
524 // Erase any MaybeDeadCopies whose destination register is clobbered.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
525 for (SmallSetVector<MachineInstr *, 8>::iterator DI =
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
526 MaybeDeadCopies.begin();
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
527 DI != MaybeDeadCopies.end();) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
528 MachineInstr *MaybeDead = *DI;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
529 unsigned Reg = MaybeDead->getOperand(0).getReg();
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
530 assert(!MRI->isReserved(Reg));
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
531
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
532 if (!RegMask->clobbersPhysReg(Reg)) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
533 ++DI;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
534 continue;
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
535 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
536
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
537 DEBUG(dbgs() << "MCP: Removing copy due to regmask clobbering: ";
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
538 MaybeDead->dump());
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
539
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
540 // erase() will return the next valid iterator pointing to the next
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
541 // element after the erased one.
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
542 DI = MaybeDeadCopies.erase(DI);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
543 MaybeDead->eraseFromParent();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
544 Changed = true;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
545 ++NumDeletes;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
546 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
547
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
548 removeClobberedRegsFromMap(AvailCopyMap, *RegMask);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
549 removeClobberedRegsFromMap(CopyMap, *RegMask);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
550 for (SourceMap::iterator I = SrcMap.begin(), E = SrcMap.end(), Next;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
551 I != E; I = Next) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
552 Next = std::next(I);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
553 if (RegMask->clobbersPhysReg(I->first)) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
554 removeRegsFromMap(AvailCopyMap, I->second, *TRI);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
555 SrcMap.erase(I);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
556 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
557 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
558 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
559
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
560 // Any previous copy definition or reading the Defs is no longer available.
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
561 for (unsigned Reg : Defs)
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
562 ClobberRegister(Reg);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
563 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
564
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
565 // If MBB doesn't have successors, delete the copies whose defs are not used.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
566 // If MBB does have successors, then conservative assume the defs are live-out
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
567 // since we don't want to trust live-in lists.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
568 if (MBB.succ_empty()) {
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
569 for (MachineInstr *MaybeDead : MaybeDeadCopies) {
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
570 DEBUG(dbgs() << "MCP: Removing copy due to no live-out succ: ";
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
571 MaybeDead->dump());
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
572 assert(!MRI->isReserved(MaybeDead->getOperand(0).getReg()));
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
573 MaybeDead->eraseFromParent();
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
574 Changed = true;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
575 ++NumDeletes;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
576 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
577 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
578
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
579 MaybeDeadCopies.clear();
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
580 AvailCopyMap.clear();
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
581 CopyMap.clear();
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
582 SrcMap.clear();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
583 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
584
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
585 bool MachineCopyPropagation::runOnMachineFunction(MachineFunction &MF) {
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
586 if (skipFunction(MF.getFunction()))
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
587 return false;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
588
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
589 Changed = false;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
590
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
591 TRI = MF.getSubtarget().getRegisterInfo();
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
592 TII = MF.getSubtarget().getInstrInfo();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
593 MRI = &MF.getRegInfo();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
594
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
595 for (MachineBasicBlock &MBB : MF)
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
596 CopyPropagateBlock(MBB);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
597
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
598 return Changed;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
599 }