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annotate lib/CodeGen/ProcessImplicitDefs.cpp @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
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1 //===---------------------- ProcessImplicitDefs.cpp -----------------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 #include "llvm/ADT/SetVector.h"
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11 #include "llvm/Analysis/AliasAnalysis.h"
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12 #include "llvm/CodeGen/MachineFunctionPass.h"
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13 #include "llvm/CodeGen/MachineInstr.h"
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14 #include "llvm/CodeGen/MachineRegisterInfo.h"
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15 #include "llvm/CodeGen/Passes.h"
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16 #include "llvm/CodeGen/TargetInstrInfo.h"
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17 #include "llvm/CodeGen/TargetSubtargetInfo.h"
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18 #include "llvm/Support/Debug.h"
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19 #include "llvm/Support/raw_ostream.h"
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20
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21 using namespace llvm;
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22
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23 #define DEBUG_TYPE "processimpdefs"
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25 namespace {
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26 /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
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27 /// for each use. Add isUndef marker to implicit_def defs and their uses.
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28 class ProcessImplicitDefs : public MachineFunctionPass {
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29 const TargetInstrInfo *TII;
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30 const TargetRegisterInfo *TRI;
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31 MachineRegisterInfo *MRI;
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32
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33 SmallSetVector<MachineInstr*, 16> WorkList;
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34
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35 void processImplicitDef(MachineInstr *MI);
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36 bool canTurnIntoImplicitDef(MachineInstr *MI);
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37
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38 public:
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39 static char ID;
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40
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41 ProcessImplicitDefs() : MachineFunctionPass(ID) {
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42 initializeProcessImplicitDefsPass(*PassRegistry::getPassRegistry());
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43 }
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44
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45 void getAnalysisUsage(AnalysisUsage &au) const override;
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46
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47 bool runOnMachineFunction(MachineFunction &fn) override;
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48 };
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49 } // end anonymous namespace
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50
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51 char ProcessImplicitDefs::ID = 0;
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52 char &llvm::ProcessImplicitDefsID = ProcessImplicitDefs::ID;
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53
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54 INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE,
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55 "Process Implicit Definitions", false, false)
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56
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57 void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
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58 AU.setPreservesCFG();
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59 AU.addPreserved<AAResultsWrapperPass>();
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60 MachineFunctionPass::getAnalysisUsage(AU);
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61 }
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62
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63 bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
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64 if (!MI->isCopyLike() &&
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65 !MI->isInsertSubreg() &&
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66 !MI->isRegSequence() &&
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67 !MI->isPHI())
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68 return false;
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69 for (const MachineOperand &MO : MI->operands())
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70 if (MO.isReg() && MO.isUse() && MO.readsReg())
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71 return false;
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72 return true;
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73 }
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74
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75 void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
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76 DEBUG(dbgs() << "Processing " << *MI);
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77 unsigned Reg = MI->getOperand(0).getReg();
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78
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79 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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80 // For virtual registers, mark all uses as <undef>, and convert users to
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81 // implicit-def when possible.
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82 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
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83 MO.setIsUndef();
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84 MachineInstr *UserMI = MO.getParent();
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85 if (!canTurnIntoImplicitDef(UserMI))
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86 continue;
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87 DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
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88 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
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89 WorkList.insert(UserMI);
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90 }
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91 MI->eraseFromParent();
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92 return;
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93 }
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94
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95 // This is a physreg implicit-def.
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96 // Look for the first instruction to use or define an alias.
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97 MachineBasicBlock::instr_iterator UserMI = MI->getIterator();
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98 MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end();
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99 bool Found = false;
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100 for (++UserMI; UserMI != UserE; ++UserMI) {
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101 for (MachineOperand &MO : UserMI->operands()) {
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102 if (!MO.isReg())
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103 continue;
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104 unsigned UserReg = MO.getReg();
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105 if (!TargetRegisterInfo::isPhysicalRegister(UserReg) ||
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106 !TRI->regsOverlap(Reg, UserReg))
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107 continue;
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108 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
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109 Found = true;
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110 if (MO.isUse())
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111 MO.setIsUndef();
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112 }
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113 if (Found)
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114 break;
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115 }
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116
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117 // If we found the using MI, we can erase the IMPLICIT_DEF.
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118 if (Found) {
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119 DEBUG(dbgs() << "Physreg user: " << *UserMI);
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120 MI->eraseFromParent();
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121 return;
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122 }
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123
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124 // Using instr wasn't found, it could be in another block.
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125 // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
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126 for (unsigned i = MI->getNumOperands() - 1; i; --i)
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127 MI->RemoveOperand(i);
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128 DEBUG(dbgs() << "Keeping physreg: " << *MI);
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129 }
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130
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131 /// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
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132 /// <undef> operands.
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133 bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
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134
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135 DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
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136 << "********** Function: " << MF.getName() << '\n');
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137
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138 bool Changed = false;
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139
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140 TII = MF.getSubtarget().getInstrInfo();
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141 TRI = MF.getSubtarget().getRegisterInfo();
0
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142 MRI = &MF.getRegInfo();
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143 assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
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144 assert(WorkList.empty() && "Inconsistent worklist state");
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145
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146 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end();
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147 MFI != MFE; ++MFI) {
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148 // Scan the basic block for implicit defs.
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149 for (MachineBasicBlock::instr_iterator MBBI = MFI->instr_begin(),
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150 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI)
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151 if (MBBI->isImplicitDef())
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152 WorkList.insert(&*MBBI);
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153
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154 if (WorkList.empty())
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155 continue;
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156
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157 DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size()
0
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158 << " implicit defs.\n");
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159 Changed = true;
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160
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161 // Drain the WorkList to recursively process any new implicit defs.
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162 do processImplicitDef(WorkList.pop_back_val());
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163 while (!WorkList.empty());
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164 }
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165 return Changed;
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166 }