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annotate lib/CodeGen/RegAllocBasic.cpp @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
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1 //===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the RABasic function pass, which provides a minimal
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11 // implementation of the basic register allocator.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 #include "AllocationOrder.h"
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16 #include "LiveDebugVariables.h"
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17 #include "RegAllocBase.h"
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18 #include "Spiller.h"
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19 #include "llvm/Analysis/AliasAnalysis.h"
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20 #include "llvm/CodeGen/CalcSpillWeights.h"
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21 #include "llvm/CodeGen/LiveIntervals.h"
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22 #include "llvm/CodeGen/LiveRangeEdit.h"
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23 #include "llvm/CodeGen/LiveRegMatrix.h"
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24 #include "llvm/CodeGen/LiveStacks.h"
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25 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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26 #include "llvm/CodeGen/MachineFunctionPass.h"
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27 #include "llvm/CodeGen/MachineInstr.h"
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28 #include "llvm/CodeGen/MachineLoopInfo.h"
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29 #include "llvm/CodeGen/MachineRegisterInfo.h"
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30 #include "llvm/CodeGen/Passes.h"
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31 #include "llvm/CodeGen/RegAllocRegistry.h"
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32 #include "llvm/CodeGen/TargetRegisterInfo.h"
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33 #include "llvm/CodeGen/VirtRegMap.h"
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34 #include "llvm/PassAnalysisSupport.h"
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35 #include "llvm/Support/Debug.h"
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36 #include "llvm/Support/raw_ostream.h"
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37 #include <cstdlib>
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38 #include <queue>
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39
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40 using namespace llvm;
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41
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42 #define DEBUG_TYPE "regalloc"
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43
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44 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
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45 createBasicRegisterAllocator);
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46
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47 namespace {
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48 struct CompSpillWeight {
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49 bool operator()(LiveInterval *A, LiveInterval *B) const {
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50 return A->weight < B->weight;
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51 }
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52 };
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53 }
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54
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55 namespace {
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56 /// RABasic provides a minimal implementation of the basic register allocation
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57 /// algorithm. It prioritizes live virtual registers by spill weight and spills
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58 /// whenever a register is unavailable. This is not practical in production but
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59 /// provides a useful baseline both for measuring other allocators and comparing
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60 /// the speed of the basic algorithm against other styles of allocators.
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61 class RABasic : public MachineFunctionPass,
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62 public RegAllocBase,
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63 private LiveRangeEdit::Delegate {
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64 // context
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65 MachineFunction *MF;
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66
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67 // state
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68 std::unique_ptr<Spiller> SpillerInstance;
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69 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
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70 CompSpillWeight> Queue;
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71
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72 // Scratch space. Allocated here to avoid repeated malloc calls in
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73 // selectOrSplit().
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74 BitVector UsableRegs;
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75
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76 bool LRE_CanEraseVirtReg(unsigned) override;
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77 void LRE_WillShrinkVirtReg(unsigned) override;
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78
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79 public:
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80 RABasic();
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81
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82 /// Return the pass name.
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83 StringRef getPassName() const override { return "Basic Register Allocator"; }
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84
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85 /// RABasic analysis usage.
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86 void getAnalysisUsage(AnalysisUsage &AU) const override;
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87
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88 void releaseMemory() override;
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89
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90 Spiller &spiller() override { return *SpillerInstance; }
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91
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92 void enqueue(LiveInterval *LI) override {
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93 Queue.push(LI);
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94 }
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96 LiveInterval *dequeue() override {
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97 if (Queue.empty())
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98 return nullptr;
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99 LiveInterval *LI = Queue.top();
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100 Queue.pop();
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101 return LI;
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102 }
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103
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104 unsigned selectOrSplit(LiveInterval &VirtReg,
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105 SmallVectorImpl<unsigned> &SplitVRegs) override;
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106
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107 /// Perform register allocation.
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108 bool runOnMachineFunction(MachineFunction &mf) override;
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109
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110 MachineFunctionProperties getRequiredProperties() const override {
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111 return MachineFunctionProperties().set(
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112 MachineFunctionProperties::Property::NoPHIs);
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113 }
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114
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115 // Helper for spilling all live virtual registers currently unified under preg
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116 // that interfere with the most recently queried lvr. Return true if spilling
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117 // was successful, and append any new spilled/split intervals to splitLVRs.
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118 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
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119 SmallVectorImpl<unsigned> &SplitVRegs);
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120
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121 static char ID;
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122 };
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123
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124 char RABasic::ID = 0;
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125
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126 } // end anonymous namespace
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127
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128 char &llvm::RABasicID = RABasic::ID;
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129
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130 INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator",
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131 false, false)
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132 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
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133 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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134 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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135 INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
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136 INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
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137 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
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138 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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139 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
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140 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
141 INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
142 INITIALIZE_PASS_END(RABasic, "regallocbasic", "Basic Register Allocator", false,
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
143 false)
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
144
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
145 bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
146 LiveInterval &LI = LIS->getInterval(VirtReg);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
147 if (VRM->hasPhys(VirtReg)) {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
148 Matrix->unassign(LI);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
149 aboutToRemoveInterval(LI);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
150 return true;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
151 }
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
152 // Unassigned virtreg is probably in the priority queue.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
153 // RegAllocBase will erase it after dequeueing.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
154 // Nonetheless, clear the live-range so that the debug
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
155 // dump will show the right state for that VirtReg.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
156 LI.clear();
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
157 return false;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
158 }
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
159
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
160 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
161 if (!VRM->hasPhys(VirtReg))
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
162 return;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
163
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
164 // Register is assigned, put it back on the queue for reassignment.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
165 LiveInterval &LI = LIS->getInterval(VirtReg);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
166 Matrix->unassign(LI);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
167 enqueue(&LI);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
168 }
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
169
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 RABasic::RABasic(): MachineFunctionPass(ID) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
171 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
172
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
173 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 AU.setPreservesCFG();
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
175 AU.addRequired<AAResultsWrapperPass>();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
176 AU.addPreserved<AAResultsWrapperPass>();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
177 AU.addRequired<LiveIntervals>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
178 AU.addPreserved<LiveIntervals>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
179 AU.addPreserved<SlotIndexes>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
180 AU.addRequired<LiveDebugVariables>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
181 AU.addPreserved<LiveDebugVariables>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 AU.addRequired<LiveStacks>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 AU.addPreserved<LiveStacks>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 AU.addRequired<MachineBlockFrequencyInfo>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 AU.addPreserved<MachineBlockFrequencyInfo>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 AU.addRequiredID(MachineDominatorsID);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
187 AU.addPreservedID(MachineDominatorsID);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
188 AU.addRequired<MachineLoopInfo>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
189 AU.addPreserved<MachineLoopInfo>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
190 AU.addRequired<VirtRegMap>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
191 AU.addPreserved<VirtRegMap>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 AU.addRequired<LiveRegMatrix>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
193 AU.addPreserved<LiveRegMatrix>();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
194 MachineFunctionPass::getAnalysisUsage(AU);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
195 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
196
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
197 void RABasic::releaseMemory() {
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
198 SpillerInstance.reset();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
199 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
200
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
201
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
202 // Spill or split all live virtual registers currently unified under PhysReg
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
203 // that interfere with VirtReg. The newly spilled or split live intervals are
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
204 // returned by appending them to SplitVRegs.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
205 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
206 SmallVectorImpl<unsigned> &SplitVRegs) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
207 // Record each interference and determine if all are spillable before mutating
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
208 // either the union or live intervals.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
209 SmallVector<LiveInterval*, 8> Intfs;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
210
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
211 // Collect interferences assigned to any alias of the physical register.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
212 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
213 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
214 Q.collectInterferingVRegs();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
215 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
216 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
217 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
218 return false;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
219 Intfs.push_back(Intf);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
220 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
221 }
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
222 DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI)
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
223 << " interferences with " << VirtReg << "\n");
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
224 assert(!Intfs.empty() && "expected interference");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
225
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
226 // Spill each interfering vreg allocated to PhysReg or an alias.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
227 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
228 LiveInterval &Spill = *Intfs[i];
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
229
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
230 // Skip duplicates.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
231 if (!VRM->hasPhys(Spill.reg))
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
232 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
233
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
234 // Deallocate the interfering vreg by removing it from the union.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
235 // A LiveInterval instance may not be in a union during modification!
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
236 Matrix->unassign(Spill);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
237
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
238 // Spill the extracted interval.
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
239 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
240 spiller().spill(LRE);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
241 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
242 return true;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
243 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
244
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
245 // Driver for the register assignment and splitting heuristics.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
246 // Manages iteration over the LiveIntervalUnions.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
247 //
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
248 // This is a minimal implementation of register assignment and splitting that
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
249 // spills whenever we run out of registers.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
250 //
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 // selectOrSplit can only be called once per live virtual register. We then do a
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
252 // single interference test for each register the correct class until we find an
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 // available register. So, the number of interference tests in the worst case is
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
254 // |vregs| * |machineregs|. And since the number of interference tests is
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
255 // minimal, there is no value in caching them outside the scope of
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
256 // selectOrSplit().
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
257 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
258 SmallVectorImpl<unsigned> &SplitVRegs) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
259 // Populate a list of physical register spill candidates.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
260 SmallVector<unsigned, 8> PhysRegSpillCands;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
261
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
262 // Check for an available register in this class.
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
263 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
264 while (unsigned PhysReg = Order.next()) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
265 // Check for interference in PhysReg
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
266 switch (Matrix->checkInterference(VirtReg, PhysReg)) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
267 case LiveRegMatrix::IK_Free:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
268 // PhysReg is available, allocate it.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
269 return PhysReg;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
270
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
271 case LiveRegMatrix::IK_VirtReg:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
272 // Only virtual registers in the way, we may be able to spill them.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
273 PhysRegSpillCands.push_back(PhysReg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
274 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
275
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
276 default:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
277 // RegMask or RegUnit interference.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
278 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
279 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
280 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
281
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
282 // Try to spill another interfering reg with less spill weight.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
283 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
284 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
285 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
286 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
287
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
288 assert(!Matrix->checkInterference(VirtReg, *PhysRegI) &&
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
289 "Interference after spill.");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
290 // Tell the caller to allocate to this newly freed physical register.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
291 return *PhysRegI;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
292 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
293
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
294 // No other spill candidates were found, so spill the current VirtReg.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
295 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
296 if (!VirtReg.isSpillable())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
297 return ~0u;
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
298 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
299 spiller().spill(LRE);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
300
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
301 // The live virtual register requesting allocation was spilled, so tell
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
302 // the caller not to allocate anything during this round.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
303 return 0;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
304 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
305
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
306 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
307 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
308 << "********** Function: "
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
309 << mf.getName() << '\n');
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
310
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
311 MF = &mf;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
312 RegAllocBase::init(getAnalysis<VirtRegMap>(),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
313 getAnalysis<LiveIntervals>(),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
314 getAnalysis<LiveRegMatrix>());
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
315
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
316 calculateSpillWeightsAndHints(*LIS, *MF, VRM,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
317 getAnalysis<MachineLoopInfo>(),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
318 getAnalysis<MachineBlockFrequencyInfo>());
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
319
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
320 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
321
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
322 allocatePhysRegs();
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
323 postOptimization();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
324
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
325 // Diagnostic output before rewriting
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
326 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
327
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
328 releaseMemory();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
329 return true;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
330 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
331
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
332 FunctionPass* llvm::createBasicRegisterAllocator()
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
333 {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
334 return new RABasic();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
335 }