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120
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1 //===-- RenameIndependentSubregs.cpp - Live Interval Analysis -------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 /// Rename independent subregisters looks for virtual registers with
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11 /// independently used subregisters and renames them to new virtual registers.
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12 /// Example: In the following:
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134
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13 /// %0:sub0<read-undef> = ...
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14 /// %0:sub1 = ...
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15 /// use %0:sub0
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16 /// %0:sub0 = ...
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17 /// use %0:sub0
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18 /// use %0:sub1
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120
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19 /// sub0 and sub1 are never used together, and we have two independent sub0
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20 /// definitions. This pass will rename to:
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134
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21 /// %0:sub0<read-undef> = ...
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22 /// %1:sub1<read-undef> = ...
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23 /// use %1:sub1
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24 /// %2:sub1<read-undef> = ...
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25 /// use %2:sub1
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26 /// use %0:sub0
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120
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27 //
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28 //===----------------------------------------------------------------------===//
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29
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30 #include "LiveRangeUtils.h"
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31 #include "PHIEliminationUtils.h"
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32 #include "llvm/CodeGen/LiveInterval.h"
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134
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33 #include "llvm/CodeGen/LiveIntervals.h"
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120
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34 #include "llvm/CodeGen/MachineFunctionPass.h"
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121
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35 #include "llvm/CodeGen/MachineInstrBuilder.h"
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120
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36 #include "llvm/CodeGen/MachineRegisterInfo.h"
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37 #include "llvm/CodeGen/Passes.h"
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134
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38 #include "llvm/CodeGen/TargetInstrInfo.h"
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120
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39
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40 using namespace llvm;
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41
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42 #define DEBUG_TYPE "rename-independent-subregs"
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43
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44 namespace {
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45
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46 class RenameIndependentSubregs : public MachineFunctionPass {
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47 public:
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48 static char ID;
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49 RenameIndependentSubregs() : MachineFunctionPass(ID) {}
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50
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51 StringRef getPassName() const override {
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52 return "Rename Disconnected Subregister Components";
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53 }
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54
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55 void getAnalysisUsage(AnalysisUsage &AU) const override {
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56 AU.setPreservesCFG();
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57 AU.addRequired<LiveIntervals>();
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58 AU.addPreserved<LiveIntervals>();
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59 AU.addRequired<SlotIndexes>();
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60 AU.addPreserved<SlotIndexes>();
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61 MachineFunctionPass::getAnalysisUsage(AU);
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62 }
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63
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64 bool runOnMachineFunction(MachineFunction &MF) override;
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65
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66 private:
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67 struct SubRangeInfo {
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68 ConnectedVNInfoEqClasses ConEQ;
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69 LiveInterval::SubRange *SR;
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70 unsigned Index;
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71
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72 SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &SR,
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73 unsigned Index)
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74 : ConEQ(LIS), SR(&SR), Index(Index) {}
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75 };
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76
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77 /// Split unrelated subregister components and rename them to new vregs.
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78 bool renameComponents(LiveInterval &LI) const;
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79
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80 /// \brief Build a vector of SubRange infos and a union find set of
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81 /// equivalence classes.
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82 /// Returns true if more than 1 equivalence class was found.
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83 bool findComponents(IntEqClasses &Classes,
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84 SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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85 LiveInterval &LI) const;
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86
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87 /// \brief Distribute the LiveInterval segments into the new LiveIntervals
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88 /// belonging to their class.
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89 void distribute(const IntEqClasses &Classes,
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90 const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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91 const SmallVectorImpl<LiveInterval*> &Intervals) const;
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92
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93 /// \brief Constructs main liverange and add missing undef+dead flags.
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94 void computeMainRangesFixFlags(const IntEqClasses &Classes,
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95 const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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96 const SmallVectorImpl<LiveInterval*> &Intervals) const;
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97
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98 /// Rewrite Machine Operands to use the new vreg belonging to their class.
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99 void rewriteOperands(const IntEqClasses &Classes,
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100 const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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101 const SmallVectorImpl<LiveInterval*> &Intervals) const;
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102
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103
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104 LiveIntervals *LIS;
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105 MachineRegisterInfo *MRI;
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106 const TargetInstrInfo *TII;
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107 };
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108
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109 } // end anonymous namespace
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110
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111 char RenameIndependentSubregs::ID;
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112
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113 char &llvm::RenameIndependentSubregsID = RenameIndependentSubregs::ID;
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114
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121
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115 INITIALIZE_PASS_BEGIN(RenameIndependentSubregs, DEBUG_TYPE,
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120
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116 "Rename Independent Subregisters", false, false)
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117 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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118 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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121
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119 INITIALIZE_PASS_END(RenameIndependentSubregs, DEBUG_TYPE,
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120
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120 "Rename Independent Subregisters", false, false)
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121
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122 bool RenameIndependentSubregs::renameComponents(LiveInterval &LI) const {
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123 // Shortcut: We cannot have split components with a single definition.
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124 if (LI.valnos.size() < 2)
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125 return false;
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126
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127 SmallVector<SubRangeInfo, 4> SubRangeInfos;
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128 IntEqClasses Classes;
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129 if (!findComponents(Classes, SubRangeInfos, LI))
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130 return false;
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131
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132 // Create a new VReg for each class.
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133 unsigned Reg = LI.reg;
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134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
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135 SmallVector<LiveInterval*, 4> Intervals;
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136 Intervals.push_back(&LI);
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134
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137 DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses()
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120
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138 << " equivalence classes.\n");
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134
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139 DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:");
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120
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140 for (unsigned I = 1, NumClasses = Classes.getNumClasses(); I < NumClasses;
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141 ++I) {
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142 unsigned NewVReg = MRI->createVirtualRegister(RegClass);
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143 LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg);
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144 Intervals.push_back(&NewLI);
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134
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145 DEBUG(dbgs() << ' ' << printReg(NewVReg));
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120
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146 }
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147 DEBUG(dbgs() << '\n');
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148
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149 rewriteOperands(Classes, SubRangeInfos, Intervals);
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150 distribute(Classes, SubRangeInfos, Intervals);
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151 computeMainRangesFixFlags(Classes, SubRangeInfos, Intervals);
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152 return true;
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153 }
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154
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155 bool RenameIndependentSubregs::findComponents(IntEqClasses &Classes,
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156 SmallVectorImpl<RenameIndependentSubregs::SubRangeInfo> &SubRangeInfos,
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157 LiveInterval &LI) const {
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158 // First step: Create connected components for the VNInfos inside the
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159 // subranges and count the global number of such components.
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160 unsigned NumComponents = 0;
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161 for (LiveInterval::SubRange &SR : LI.subranges()) {
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162 SubRangeInfos.push_back(SubRangeInfo(*LIS, SR, NumComponents));
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163 ConnectedVNInfoEqClasses &ConEQ = SubRangeInfos.back().ConEQ;
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164
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165 unsigned NumSubComponents = ConEQ.Classify(SR);
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166 NumComponents += NumSubComponents;
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167 }
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168 // Shortcut: With only 1 subrange, the normal separate component tests are
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169 // enough and we do not need to perform the union-find on the subregister
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170 // segments.
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171 if (SubRangeInfos.size() < 2)
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172 return false;
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173
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174 // Next step: Build union-find structure over all subranges and merge classes
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175 // across subranges when they are affected by the same MachineOperand.
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176 const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
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177 Classes.grow(NumComponents);
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178 unsigned Reg = LI.reg;
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179 for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
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180 if (!MO.isDef() && !MO.readsReg())
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181 continue;
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182 unsigned SubRegIdx = MO.getSubReg();
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183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
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184 unsigned MergedID = ~0u;
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185 for (RenameIndependentSubregs::SubRangeInfo &SRInfo : SubRangeInfos) {
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186 const LiveInterval::SubRange &SR = *SRInfo.SR;
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121
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187 if ((SR.LaneMask & LaneMask).none())
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120
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188 continue;
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189 SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
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190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
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191 : Pos.getBaseIndex();
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192 const VNInfo *VNI = SR.getVNInfoAt(Pos);
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193 if (VNI == nullptr)
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194 continue;
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195
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196 // Map to local representant ID.
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197 unsigned LocalID = SRInfo.ConEQ.getEqClass(VNI);
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198 // Global ID
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199 unsigned ID = LocalID + SRInfo.Index;
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200 // Merge other sets
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201 MergedID = MergedID == ~0u ? ID : Classes.join(MergedID, ID);
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202 }
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203 }
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204
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205 // Early exit if we ended up with a single equivalence class.
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206 Classes.compress();
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207 unsigned NumClasses = Classes.getNumClasses();
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208 return NumClasses > 1;
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209 }
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210
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211 void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes,
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212 const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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213 const SmallVectorImpl<LiveInterval*> &Intervals) const {
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214 const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
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121
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215 unsigned Reg = Intervals[0]->reg;
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120
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216 for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg),
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217 E = MRI->reg_nodbg_end(); I != E; ) {
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218 MachineOperand &MO = *I++;
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219 if (!MO.isDef() && !MO.readsReg())
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220 continue;
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221
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222 SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
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223 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
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224 : Pos.getBaseIndex();
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225 unsigned SubRegIdx = MO.getSubReg();
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226 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
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227
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228 unsigned ID = ~0u;
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229 for (const SubRangeInfo &SRInfo : SubRangeInfos) {
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230 const LiveInterval::SubRange &SR = *SRInfo.SR;
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121
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231 if ((SR.LaneMask & LaneMask).none())
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120
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232 continue;
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233 const VNInfo *VNI = SR.getVNInfoAt(Pos);
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234 if (VNI == nullptr)
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235 continue;
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236
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237 // Map to local representant ID.
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238 unsigned LocalID = SRInfo.ConEQ.getEqClass(VNI);
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239 // Global ID
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240 ID = Classes[LocalID + SRInfo.Index];
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241 break;
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242 }
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243
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244 unsigned VReg = Intervals[ID]->reg;
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245 MO.setReg(VReg);
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121
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246
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247 if (MO.isTied() && Reg != VReg) {
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248 /// Undef use operands are not tracked in the equivalence class but need
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249 /// to be update if they are tied.
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250 MO.getParent()->substituteRegister(Reg, VReg, 0, TRI);
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251
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252 // substituteRegister breaks the iterator, so restart.
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253 I = MRI->reg_nodbg_begin(Reg);
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254 }
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120
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255 }
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256 // TODO: We could attempt to recompute new register classes while visiting
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257 // the operands: Some of the split register may be fine with less constraint
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258 // classes than the original vreg.
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259 }
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260
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261 void RenameIndependentSubregs::distribute(const IntEqClasses &Classes,
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262 const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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263 const SmallVectorImpl<LiveInterval*> &Intervals) const {
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264 unsigned NumClasses = Classes.getNumClasses();
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265 SmallVector<unsigned, 8> VNIMapping;
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266 SmallVector<LiveInterval::SubRange*, 8> SubRanges;
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267 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
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268 for (const SubRangeInfo &SRInfo : SubRangeInfos) {
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269 LiveInterval::SubRange &SR = *SRInfo.SR;
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270 unsigned NumValNos = SR.valnos.size();
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271 VNIMapping.clear();
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272 VNIMapping.reserve(NumValNos);
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273 SubRanges.clear();
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274 SubRanges.resize(NumClasses-1, nullptr);
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275 for (unsigned I = 0; I < NumValNos; ++I) {
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276 const VNInfo &VNI = *SR.valnos[I];
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277 unsigned LocalID = SRInfo.ConEQ.getEqClass(&VNI);
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278 unsigned ID = Classes[LocalID + SRInfo.Index];
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279 VNIMapping.push_back(ID);
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280 if (ID > 0 && SubRanges[ID-1] == nullptr)
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281 SubRanges[ID-1] = Intervals[ID]->createSubRange(Allocator, SR.LaneMask);
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282 }
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283 DistributeRange(SR, SubRanges.data(), VNIMapping);
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284 }
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285 }
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286
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287 static bool subRangeLiveAt(const LiveInterval &LI, SlotIndex Pos) {
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288 for (const LiveInterval::SubRange &SR : LI.subranges()) {
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289 if (SR.liveAt(Pos))
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290 return true;
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291 }
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292 return false;
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293 }
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294
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295 void RenameIndependentSubregs::computeMainRangesFixFlags(
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296 const IntEqClasses &Classes,
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297 const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
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298 const SmallVectorImpl<LiveInterval*> &Intervals) const {
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299 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
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300 const SlotIndexes &Indexes = *LIS->getSlotIndexes();
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301 for (size_t I = 0, E = Intervals.size(); I < E; ++I) {
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302 LiveInterval &LI = *Intervals[I];
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303 unsigned Reg = LI.reg;
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304
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305 LI.removeEmptySubRanges();
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306
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307 // There must be a def (or live-in) before every use. Splitting vregs may
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308 // violate this principle as the splitted vreg may not have a definition on
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309 // every path. Fix this by creating IMPLICIT_DEF instruction as necessary.
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310 for (const LiveInterval::SubRange &SR : LI.subranges()) {
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311 // Search for "PHI" value numbers in the subranges. We must find a live
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312 // value in each predecessor block, add an IMPLICIT_DEF where it is
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313 // missing.
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314 for (unsigned I = 0; I < SR.valnos.size(); ++I) {
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315 const VNInfo &VNI = *SR.valnos[I];
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316 if (VNI.isUnused() || !VNI.isPHIDef())
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317 continue;
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318
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319 SlotIndex Def = VNI.def;
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320 MachineBasicBlock &MBB = *Indexes.getMBBFromIndex(Def);
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321 for (MachineBasicBlock *PredMBB : MBB.predecessors()) {
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322 SlotIndex PredEnd = Indexes.getMBBEndIdx(PredMBB);
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323 if (subRangeLiveAt(LI, PredEnd.getPrevSlot()))
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324 continue;
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325
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326 MachineBasicBlock::iterator InsertPos =
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327 llvm::findPHICopyInsertPoint(PredMBB, &MBB, Reg);
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328 const MCInstrDesc &MCDesc = TII->get(TargetOpcode::IMPLICIT_DEF);
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329 MachineInstrBuilder ImpDef = BuildMI(*PredMBB, InsertPos,
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330 DebugLoc(), MCDesc, Reg);
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331 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef);
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332 SlotIndex RegDefIdx = DefIdx.getRegSlot();
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333 for (LiveInterval::SubRange &SR : LI.subranges()) {
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334 VNInfo *SRVNI = SR.getNextValue(RegDefIdx, Allocator);
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335 SR.addSegment(LiveRange::Segment(RegDefIdx, PredEnd, SRVNI));
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336 }
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337 }
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338 }
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339 }
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340
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341 for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
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342 if (!MO.isDef())
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343 continue;
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344 unsigned SubRegIdx = MO.getSubReg();
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345 if (SubRegIdx == 0)
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346 continue;
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347 // After assigning the new vreg we may not have any other sublanes living
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348 // in and out of the instruction anymore. We need to add new dead and
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349 // undef flags in these cases.
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350 if (!MO.isUndef()) {
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351 SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
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352 if (!subRangeLiveAt(LI, Pos))
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353 MO.setIsUndef();
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354 }
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355 if (!MO.isDead()) {
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356 SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent()).getDeadSlot();
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357 if (!subRangeLiveAt(LI, Pos))
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358 MO.setIsDead();
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359 }
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360 }
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361
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362 if (I == 0)
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363 LI.clear();
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364 LIS->constructMainRangeFromSubranges(LI);
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365 // A def of a subregister may be a use of other register lanes. Replacing
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366 // such a def with a def of a different register will eliminate the use,
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367 // and may cause the recorded live range to be larger than the actual
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368 // liveness in the program IR.
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369 LIS->shrinkToUses(&LI);
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370 }
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371 }
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372
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373 bool RenameIndependentSubregs::runOnMachineFunction(MachineFunction &MF) {
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374 // Skip renaming if liveness of subregister is not tracked.
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375 MRI = &MF.getRegInfo();
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376 if (!MRI->subRegLivenessEnabled())
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377 return false;
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378
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379 DEBUG(dbgs() << "Renaming independent subregister live ranges in "
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380 << MF.getName() << '\n');
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381
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382 LIS = &getAnalysis<LiveIntervals>();
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383 TII = MF.getSubtarget().getInstrInfo();
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384
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385 // Iterate over all vregs. Note that we query getNumVirtRegs() the newly
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386 // created vregs end up with higher numbers but do not need to be visited as
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387 // there can't be any further splitting.
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388 bool Changed = false;
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389 for (size_t I = 0, E = MRI->getNumVirtRegs(); I < E; ++I) {
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390 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
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391 if (!LIS->hasInterval(Reg))
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392 continue;
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393 LiveInterval &LI = LIS->getInterval(Reg);
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394 if (!LI.hasSubRanges())
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395 continue;
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396
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397 Changed |= renameComponents(LI);
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398 }
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399
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400 return Changed;
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401 }
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