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1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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121
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10 /// \file This implements the ScheduleDAGInstrs class, which implements
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11 /// re-scheduling of MachineInstrs.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
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100
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16 #include "llvm/ADT/IntEqClasses.h"
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121
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17 #include "llvm/ADT/MapVector.h"
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18 #include "llvm/ADT/SmallPtrSet.h"
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121
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19 #include "llvm/ADT/SmallVector.h"
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20 #include "llvm/ADT/SparseSet.h"
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21 #include "llvm/ADT/iterator_range.h"
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22 #include "llvm/Analysis/AliasAnalysis.h"
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23 #include "llvm/Analysis/ValueTracking.h"
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134
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24 #include "llvm/CodeGen/LiveIntervals.h"
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121
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25 #include "llvm/CodeGen/LivePhysRegs.h"
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|
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26 #include "llvm/CodeGen/MachineBasicBlock.h"
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95
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27 #include "llvm/CodeGen/MachineFrameInfo.h"
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121
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28 #include "llvm/CodeGen/MachineFunction.h"
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29 #include "llvm/CodeGen/MachineInstr.h"
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|
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30 #include "llvm/CodeGen/MachineInstrBundle.h"
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31 #include "llvm/CodeGen/MachineMemOperand.h"
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121
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32 #include "llvm/CodeGen/MachineOperand.h"
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33 #include "llvm/CodeGen/MachineRegisterInfo.h"
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34 #include "llvm/CodeGen/PseudoSourceValue.h"
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35 #include "llvm/CodeGen/RegisterPressure.h"
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121
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36 #include "llvm/CodeGen/ScheduleDAG.h"
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37 #include "llvm/CodeGen/ScheduleDFS.h"
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121
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38 #include "llvm/CodeGen/SlotIndexes.h"
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134
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39 #include "llvm/CodeGen/TargetRegisterInfo.h"
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40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
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121
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41 #include "llvm/IR/Constants.h"
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120
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42 #include "llvm/IR/Function.h"
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121
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43 #include "llvm/IR/Instruction.h"
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44 #include "llvm/IR/Instructions.h"
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45 #include "llvm/IR/Operator.h"
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120
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46 #include "llvm/IR/Type.h"
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121
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47 #include "llvm/IR/Value.h"
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48 #include "llvm/MC/LaneBitmask.h"
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49 #include "llvm/MC/MCRegisterInfo.h"
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50 #include "llvm/Support/Casting.h"
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51 #include "llvm/Support/CommandLine.h"
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121
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52 #include "llvm/Support/Compiler.h"
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53 #include "llvm/Support/Debug.h"
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121
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54 #include "llvm/Support/ErrorHandling.h"
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55 #include "llvm/Support/Format.h"
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56 #include "llvm/Support/raw_ostream.h"
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121
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57 #include <algorithm>
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58 #include <cassert>
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59 #include <iterator>
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60 #include <string>
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61 #include <utility>
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62 #include <vector>
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63
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64 using namespace llvm;
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65
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121
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66 #define DEBUG_TYPE "machine-scheduler"
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77
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67
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68 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
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69 cl::ZeroOrMore, cl::init(false),
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83
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70 cl::desc("Enable use of AA during MI DAG construction"));
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71
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77
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72 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
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83
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73 cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
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77
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74
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120
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75 // Note: the two options below might be used in tuning compile time vs
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76 // output quality. Setting HugeRegion so large that it will never be
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77 // reached means best-effort, but may be slow.
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78
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79 // When Stores and Loads maps (or NonAliasStores and NonAliasLoads)
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80 // together hold this many SUs, a reduction of maps will be done.
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81 static cl::opt<unsigned> HugeRegion("dag-maps-huge-region", cl::Hidden,
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82 cl::init(1000), cl::desc("The limit to use while constructing the DAG "
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83 "prior to scheduling, at which point a trade-off "
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84 "is made to avoid excessive compile time."));
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85
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86 static cl::opt<unsigned> ReductionSize(
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87 "dag-maps-reduction-size", cl::Hidden,
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88 cl::desc("A huge scheduling region will have maps reduced by this many "
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89 "nodes at a time. Defaults to HugeRegion / 2."));
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90
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91 static unsigned getReductionSize() {
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92 // Always reduce a huge region with half of the elements, except
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93 // when user sets this number explicitly.
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94 if (ReductionSize.getNumOccurrences() == 0)
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95 return HugeRegion / 2;
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96 return ReductionSize;
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97 }
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98
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99 static void dumpSUList(ScheduleDAGInstrs::SUList &L) {
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100 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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101 dbgs() << "{ ";
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102 for (const SUnit *su : L) {
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103 dbgs() << "SU(" << su->NodeNum << ")";
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104 if (su != L.back())
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105 dbgs() << ", ";
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106 }
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107 dbgs() << "}\n";
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108 #endif
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109 }
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110
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111 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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77
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112 const MachineLoopInfo *mli,
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100
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113 bool RemoveKillFlags)
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114 : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()),
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121
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115 RemoveKillFlags(RemoveKillFlags),
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120
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116 UnknownValue(UndefValue::get(
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134
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117 Type::getVoidTy(mf.getFunction().getContext()))) {
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118 DbgValues.clear();
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119
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120 const TargetSubtargetInfo &ST = mf.getSubtarget();
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77
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121 SchedModel.init(ST.getSchedModel(), &ST, TII);
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122 }
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123
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121
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124 /// If this machine instr has memory reference information and it can be
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125 /// tracked to a normal reference to a known object, return the Value
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126 /// for that object. This function returns false the memory location is
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127 /// unknown or may alias anything.
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128 static bool getUnderlyingObjectsForInstr(const MachineInstr *MI,
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120
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129 const MachineFrameInfo &MFI,
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95
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130 UnderlyingObjectsVector &Objects,
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131 const DataLayout &DL) {
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120
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132 auto allMMOsOkay = [&]() {
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133 for (const MachineMemOperand *MMO : MI->memoperands()) {
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134 if (MMO->isVolatile())
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135 return false;
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136
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120
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137 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
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138 // Function that contain tail calls don't have unique PseudoSourceValue
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139 // objects. Two PseudoSourceValues might refer to the same or
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140 // overlapping locations. The client code calling this function assumes
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141 // this is not the case. So return a conservative answer of no known
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142 // object.
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143 if (MFI.hasTailCall())
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144 return false;
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145
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146 // For now, ignore PseudoSourceValues which may alias LLVM IR values
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147 // because the code that uses this function has no way to cope with
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148 // such aliases.
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149 if (PSV->isAliased(&MFI))
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150 return false;
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95
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151
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120
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152 bool MayAlias = PSV->mayAlias(&MFI);
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153 Objects.push_back(UnderlyingObjectsVector::value_type(PSV, MayAlias));
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154 } else if (const Value *V = MMO->getValue()) {
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155 SmallVector<Value *, 4> Objs;
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121
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156 if (!getUnderlyingObjectsForCodeGen(V, Objs, DL))
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157 return false;
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120
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158
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159 for (Value *V : Objs) {
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121
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160 assert(isIdentifiedObject(V));
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120
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161 Objects.push_back(UnderlyingObjectsVector::value_type(V, true));
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162 }
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163 } else
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164 return false;
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165 }
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166 return true;
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167 };
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168
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121
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169 if (!allMMOsOkay()) {
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120
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170 Objects.clear();
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121
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171 return false;
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172 }
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173
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174 return true;
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175 }
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176
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177 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
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178 BB = bb;
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179 }
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180
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181 void ScheduleDAGInstrs::finishBlock() {
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182 // Subclasses should no longer refer to the old block.
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77
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183 BB = nullptr;
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184 }
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185
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186 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
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187 MachineBasicBlock::iterator begin,
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188 MachineBasicBlock::iterator end,
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189 unsigned regioninstrs) {
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190 assert(bb == BB && "startBlock should set BB");
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191 RegionBegin = begin;
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192 RegionEnd = end;
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193 NumRegionInstrs = regioninstrs;
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194 }
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195
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196 void ScheduleDAGInstrs::exitRegion() {
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197 // Nothing to do.
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198 }
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199
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200 void ScheduleDAGInstrs::addSchedBarrierDeps() {
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77
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201 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
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202 ExitSU.setInstr(ExitMI);
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120
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203 // Add dependencies on the defs and uses of the instruction.
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204 if (ExitMI) {
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205 for (const MachineOperand &MO : ExitMI->operands()) {
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206 if (!MO.isReg() || MO.isDef()) continue;
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207 unsigned Reg = MO.getReg();
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120
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208 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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209 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
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120
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210 } else if (TargetRegisterInfo::isVirtualRegister(Reg) && MO.readsReg()) {
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211 addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO));
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212 }
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213 }
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120
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214 }
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215 if (!ExitMI || (!ExitMI->isCall() && !ExitMI->isBarrier())) {
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216 // For others, e.g. fallthrough, conditional branch, assume the exit
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217 // uses all the registers that are livein to the successor blocks.
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120
|
218 for (const MachineBasicBlock *Succ : BB->successors()) {
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219 for (const auto &LI : Succ->liveins()) {
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95
|
220 if (!Uses.contains(LI.PhysReg))
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221 Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg));
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222 }
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120
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223 }
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224 }
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225 }
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226
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121
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227 /// MO is an operand of SU's instruction that defines a physical register. Adds
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228 /// data dependencies from SU to any uses of the physical register.
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229 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
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230 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
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231 assert(MO.isDef() && "expect physreg def");
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232
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233 // Ask the target if address-backscheduling is desirable, and if so how much.
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|
83
|
234 const TargetSubtargetInfo &ST = MF.getSubtarget();
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235
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236 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
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changeset
|
237 Alias.isValid(); ++Alias) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
238 if (!Uses.contains(*Alias))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
239 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
240 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
241 SUnit *UseSU = I->SU;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
242 if (UseSU == SU)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
243 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
244
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
245 // Adjust the dependence latency using operand def/use information,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
246 // then allow the target to perform its own adjustments.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
247 int UseOp = I->OpIdx;
|
|
77
|
248 MachineInstr *RegUse = nullptr;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
249 SDep Dep;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
250 if (UseOp < 0)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
251 Dep = SDep(SU, SDep::Artificial);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
252 else {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
253 // Set the hasPhysRegDefs only for physreg defs that have a use within
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
254 // the scheduling region.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
255 SU->hasPhysRegDefs = true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
256 Dep = SDep(SU, SDep::Data, *Alias);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
257 RegUse = UseSU->getInstr();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
258 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
259 Dep.setLatency(
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
260 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
261 UseOp));
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
262
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
263 ST.adjustSchedDependency(SU, UseSU, Dep);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
264 UseSU->addPred(Dep);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
265 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
266 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
267 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
268
|
|
121
|
269 /// \brief Adds register dependencies (data, anti, and output) from this SUnit
|
|
|
270 /// to following instructions in the same scheduling region that depend the
|
|
|
271 /// physical register referenced at OperIdx.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
272 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
|
|
77
|
273 MachineInstr *MI = SU->getInstr();
|
|
|
274 MachineOperand &MO = MI->getOperand(OperIdx);
|
|
120
|
275 unsigned Reg = MO.getReg();
|
|
|
276 // We do not need to track any dependencies for constant registers.
|
|
|
277 if (MRI.isConstantPhysReg(Reg))
|
|
|
278 return;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
279
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
280 // Optionally add output and anti dependencies. For anti
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
281 // dependencies we use a latency of 0 because for a multi-issue
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
282 // target we want to allow the defining instruction to issue
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
283 // in the same cycle as the using instruction.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
284 // TODO: Using a latency of 1 here for output dependencies assumes
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
285 // there's no cost for reusing registers.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
286 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
|
|
120
|
287 for (MCRegAliasIterator Alias(Reg, TRI, true); Alias.isValid(); ++Alias) {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
288 if (!Defs.contains(*Alias))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
289 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
290 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
291 SUnit *DefSU = I->SU;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
292 if (DefSU == &ExitSU)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
293 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
294 if (DefSU != SU &&
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
295 (Kind != SDep::Output || !MO.isDead() ||
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
296 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
297 if (Kind == SDep::Anti)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
298 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
299 else {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
300 SDep Dep(SU, Kind, /*Reg=*/*Alias);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
301 Dep.setLatency(
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
302 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
303 DefSU->addPred(Dep);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
304 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
305 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
306 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
307 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
308
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
309 if (!MO.isDef()) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
310 SU->hasPhysRegUses = true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
311 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
312 // retrieve the existing SUnits list for this register's uses.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
313 // Push this SUnit on the use list.
|
|
120
|
314 Uses.insert(PhysRegSUOper(SU, OperIdx, Reg));
|
|
77
|
315 if (RemoveKillFlags)
|
|
|
316 MO.setIsKill(false);
|
|
120
|
317 } else {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
318 addPhysRegDataDeps(SU, OperIdx);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
319
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
320 // clear this register's use list
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
321 if (Uses.contains(Reg))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
322 Uses.eraseAll(Reg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
323
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
324 if (!MO.isDead()) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
325 Defs.eraseAll(Reg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
326 } else if (SU->isCall) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
327 // Calls will not be reordered because of chain dependencies (see
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
328 // below). Since call operands are dead, calls may continue to be added
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
329 // to the DefList making dependence checking quadratic in the size of
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
330 // the block. Instead, we leave only one call at the back of the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
331 // DefList.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
332 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
333 Reg2SUnitsMap::iterator B = P.first;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
334 Reg2SUnitsMap::iterator I = P.second;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
335 for (bool isBegin = I == B; !isBegin; /* empty */) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
336 isBegin = (--I) == B;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
337 if (!I->SU->isCall)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
338 break;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
339 I = Defs.erase(I);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
340 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
341 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
342
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
343 // Defs are pushed in the order they are visited and never reordered.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
344 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
345 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
346 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
347
|
|
100
|
348 LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
|
|
|
349 {
|
|
|
350 unsigned Reg = MO.getReg();
|
|
|
351 // No point in tracking lanemasks if we don't have interesting subregisters.
|
|
|
352 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
|
|
|
353 if (!RC.HasDisjunctSubRegs)
|
|
121
|
354 return LaneBitmask::getAll();
|
|
100
|
355
|
|
|
356 unsigned SubReg = MO.getSubReg();
|
|
|
357 if (SubReg == 0)
|
|
|
358 return RC.getLaneMask();
|
|
|
359 return TRI->getSubRegIndexLaneMask(SubReg);
|
|
|
360 }
|
|
|
361
|
|
121
|
362 /// Adds register output and data dependencies from this SUnit to instructions
|
|
|
363 /// that occur later in the same scheduling region if they read from or write to
|
|
|
364 /// the virtual register defined at OperIdx.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
365 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
366 /// TODO: Hoist loop induction variable increments. This has to be
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
367 /// reevaluated. Generally, IV scheduling should be done before coalescing.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
368 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
|
|
100
|
369 MachineInstr *MI = SU->getInstr();
|
|
|
370 MachineOperand &MO = MI->getOperand(OperIdx);
|
|
|
371 unsigned Reg = MO.getReg();
|
|
|
372
|
|
|
373 LaneBitmask DefLaneMask;
|
|
|
374 LaneBitmask KillLaneMask;
|
|
|
375 if (TrackLaneMasks) {
|
|
|
376 bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
|
|
|
377 DefLaneMask = getLaneMaskForMO(MO);
|
|
|
378 // If we have a <read-undef> flag, none of the lane values comes from an
|
|
|
379 // earlier instruction.
|
|
121
|
380 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask;
|
|
100
|
381
|
|
|
382 // Clear undef flag, we'll re-add it later once we know which subregister
|
|
|
383 // Def is first.
|
|
|
384 MO.setIsUndef(false);
|
|
|
385 } else {
|
|
121
|
386 DefLaneMask = LaneBitmask::getAll();
|
|
|
387 KillLaneMask = LaneBitmask::getAll();
|
|
100
|
388 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
389
|
|
100
|
390 if (MO.isDead()) {
|
|
|
391 assert(CurrentVRegUses.find(Reg) == CurrentVRegUses.end() &&
|
|
|
392 "Dead defs should have no uses");
|
|
|
393 } else {
|
|
|
394 // Add data dependence to all uses we found so far.
|
|
|
395 const TargetSubtargetInfo &ST = MF.getSubtarget();
|
|
|
396 for (VReg2SUnitOperIdxMultiMap::iterator I = CurrentVRegUses.find(Reg),
|
|
|
397 E = CurrentVRegUses.end(); I != E; /*empty*/) {
|
|
|
398 LaneBitmask LaneMask = I->LaneMask;
|
|
|
399 // Ignore uses of other lanes.
|
|
121
|
400 if ((LaneMask & KillLaneMask).none()) {
|
|
100
|
401 ++I;
|
|
|
402 continue;
|
|
|
403 }
|
|
|
404
|
|
121
|
405 if ((LaneMask & DefLaneMask).any()) {
|
|
100
|
406 SUnit *UseSU = I->SU;
|
|
|
407 MachineInstr *Use = UseSU->getInstr();
|
|
|
408 SDep Dep(SU, SDep::Data, Reg);
|
|
|
409 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
|
|
|
410 I->OperandIndex));
|
|
|
411 ST.adjustSchedDependency(SU, UseSU, Dep);
|
|
|
412 UseSU->addPred(Dep);
|
|
|
413 }
|
|
|
414
|
|
|
415 LaneMask &= ~KillLaneMask;
|
|
|
416 // If we found a Def for all lanes of this use, remove it from the list.
|
|
121
|
417 if (LaneMask.any()) {
|
|
100
|
418 I->LaneMask = LaneMask;
|
|
|
419 ++I;
|
|
|
420 } else
|
|
|
421 I = CurrentVRegUses.erase(I);
|
|
|
422 }
|
|
|
423 }
|
|
|
424
|
|
|
425 // Shortcut: Singly defined vregs do not have output/anti dependencies.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
426 if (MRI.hasOneDef(Reg))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
427 return;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
428
|
|
100
|
429 // Add output dependence to the next nearest defs of this vreg.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
430 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
431 // Unless this definition is dead, the output dependence should be
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
432 // transitively redundant with antidependencies from this definition's
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
433 // uses. We're conservative for now until we have a way to guarantee the uses
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
434 // are not eliminated sometime during scheduling. The output dependence edge
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
435 // is also useful if output latency exceeds def-use latency.
|
|
100
|
436 LaneBitmask LaneMask = DefLaneMask;
|
|
|
437 for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
|
|
|
438 CurrentVRegDefs.end())) {
|
|
|
439 // Ignore defs for other lanes.
|
|
121
|
440 if ((V2SU.LaneMask & LaneMask).none())
|
|
100
|
441 continue;
|
|
|
442 // Add an output dependence.
|
|
|
443 SUnit *DefSU = V2SU.SU;
|
|
|
444 // Ignore additional defs of the same lanes in one instruction. This can
|
|
|
445 // happen because lanemasks are shared for targets with too many
|
|
|
446 // subregisters. We also use some representration tricks/hacks where we
|
|
|
447 // add super-register defs/uses, to imply that although we only access parts
|
|
|
448 // of the reg we care about the full one.
|
|
|
449 if (DefSU == SU)
|
|
|
450 continue;
|
|
|
451 SDep Dep(SU, SDep::Output, Reg);
|
|
|
452 Dep.setLatency(
|
|
|
453 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
|
|
|
454 DefSU->addPred(Dep);
|
|
|
455
|
|
|
456 // Update current definition. This can get tricky if the def was about a
|
|
|
457 // bigger lanemask before. We then have to shrink it and create a new
|
|
|
458 // VReg2SUnit for the non-overlapping part.
|
|
|
459 LaneBitmask OverlapMask = V2SU.LaneMask & LaneMask;
|
|
|
460 LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
|
|
|
461 V2SU.SU = SU;
|
|
|
462 V2SU.LaneMask = OverlapMask;
|
|
121
|
463 if (NonOverlapMask.any())
|
|
120
|
464 CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
465 }
|
|
100
|
466 // If there was no CurrentVRegDefs entry for some lanes yet, create one.
|
|
121
|
467 if (LaneMask.any())
|
|
100
|
468 CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
469 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
470
|
|
121
|
471 /// \brief Adds a register data dependency if the instruction that defines the
|
|
|
472 /// virtual register used at OperIdx is mapped to an SUnit. Add a register
|
|
|
473 /// antidependency from this SUnit to instructions that occur later in the same
|
|
|
474 /// scheduling region if they write the virtual register.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
475 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
476 /// TODO: Handle ExitSU "uses" properly.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
477 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
|
|
100
|
478 const MachineInstr *MI = SU->getInstr();
|
|
|
479 const MachineOperand &MO = MI->getOperand(OperIdx);
|
|
|
480 unsigned Reg = MO.getReg();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
481
|
|
100
|
482 // Remember the use. Data dependencies will be added when we find the def.
|
|
121
|
483 LaneBitmask LaneMask = TrackLaneMasks ? getLaneMaskForMO(MO)
|
|
|
484 : LaneBitmask::getAll();
|
|
100
|
485 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
486
|
|
100
|
487 // Add antidependences to the following defs of the vreg.
|
|
|
488 for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
|
|
|
489 CurrentVRegDefs.end())) {
|
|
|
490 // Ignore defs for unrelated lanes.
|
|
|
491 LaneBitmask PrevDefLaneMask = V2SU.LaneMask;
|
|
121
|
492 if ((PrevDefLaneMask & LaneMask).none())
|
|
100
|
493 continue;
|
|
|
494 if (V2SU.SU == SU)
|
|
|
495 continue;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
496
|
|
100
|
497 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg));
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
498 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
499 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
500
|
|
121
|
501 /// Returns true if MI is an instruction we are unable to reason about
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
502 /// (like a call or something with unmodeled side effects).
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
503 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
|
|
100
|
504 return MI->isCall() || MI->hasUnmodeledSideEffects() ||
|
|
120
|
505 (MI->hasOrderedMemoryRef() && !MI->isDereferenceableInvariantLoad(AA));
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
506 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
507
|
|
120
|
508 void ScheduleDAGInstrs::addChainDependency (SUnit *SUa, SUnit *SUb,
|
|
|
509 unsigned Latency) {
|
|
121
|
510 if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) {
|
|
120
|
511 SDep Dep(SUa, SDep::MayAliasMem);
|
|
|
512 Dep.setLatency(Latency);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
513 SUb->addPred(Dep);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
514 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
515 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
516
|
|
121
|
517 /// \brief Creates an SUnit for each real instruction, numbered in top-down
|
|
|
518 /// topological order. The instruction order A < B, implies that no edge exists
|
|
|
519 /// from B to A.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
520 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
521 /// Map each real instruction to its SUnit.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
522 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
523 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
524 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
525 /// instead of pointers.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
526 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
527 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
528 /// the original instruction list.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
529 void ScheduleDAGInstrs::initSUnits() {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
530 // We'll be allocating one SUnit for each real instruction in the region,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
531 // which is contained within a basic block.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
532 SUnits.reserve(NumRegionInstrs);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
533
|
|
121
|
534 for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) {
|
|
120
|
535 if (MI.isDebugValue())
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
536 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
537
|
|
120
|
538 SUnit *SU = newSUnit(&MI);
|
|
|
539 MISUnitMap[&MI] = SU;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
540
|
|
120
|
541 SU->isCall = MI.isCall();
|
|
|
542 SU->isCommutable = MI.isCommutable();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
543
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
544 // Assign the Latency field of SU using target-provided information.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
545 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
|
|
33
|
546
|
|
77
|
547 // If this SUnit uses a reserved or unbuffered resource, mark it as such.
|
|
|
548 //
|
|
|
549 // Reserved resources block an instruction from issuing and stall the
|
|
|
550 // entire pipeline. These are identified by BufferSize=0.
|
|
|
551 //
|
|
|
552 // Unbuffered resources prevent execution of subsequent instructions that
|
|
|
553 // require the same resources. This is used for in-order execution pipelines
|
|
|
554 // within an out-of-order core. These are identified by BufferSize=1.
|
|
33
|
555 if (SchedModel.hasInstrSchedModel()) {
|
|
|
556 const MCSchedClassDesc *SC = getSchedClass(SU);
|
|
120
|
557 for (const MCWriteProcResEntry &PRE :
|
|
|
558 make_range(SchedModel.getWriteProcResBegin(SC),
|
|
|
559 SchedModel.getWriteProcResEnd(SC))) {
|
|
|
560 switch (SchedModel.getProcResource(PRE.ProcResourceIdx)->BufferSize) {
|
|
33
|
561 case 0:
|
|
|
562 SU->hasReservedResource = true;
|
|
|
563 break;
|
|
|
564 case 1:
|
|
|
565 SU->isUnbuffered = true;
|
|
|
566 break;
|
|
|
567 default:
|
|
|
568 break;
|
|
|
569 }
|
|
|
570 }
|
|
|
571 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
572 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
573 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
574
|
|
120
|
575 class ScheduleDAGInstrs::Value2SUsMap : public MapVector<ValueType, SUList> {
|
|
|
576 /// Current total number of SUs in map.
|
|
121
|
577 unsigned NumNodes = 0;
|
|
120
|
578
|
|
|
579 /// 1 for loads, 0 for stores. (see comment in SUList)
|
|
|
580 unsigned TrueMemOrderLatency;
|
|
121
|
581
|
|
120
|
582 public:
|
|
121
|
583 Value2SUsMap(unsigned lat = 0) : TrueMemOrderLatency(lat) {}
|
|
120
|
584
|
|
|
585 /// To keep NumNodes up to date, insert() is used instead of
|
|
|
586 /// this operator w/ push_back().
|
|
|
587 ValueType &operator[](const SUList &Key) {
|
|
|
588 llvm_unreachable("Don't use. Use insert() instead."); };
|
|
|
589
|
|
121
|
590 /// Adds SU to the SUList of V. If Map grows huge, reduce its size by calling
|
|
|
591 /// reduce().
|
|
120
|
592 void inline insert(SUnit *SU, ValueType V) {
|
|
|
593 MapVector::operator[](V).push_back(SU);
|
|
|
594 NumNodes++;
|
|
|
595 }
|
|
|
596
|
|
|
597 /// Clears the list of SUs mapped to V.
|
|
|
598 void inline clearList(ValueType V) {
|
|
|
599 iterator Itr = find(V);
|
|
|
600 if (Itr != end()) {
|
|
121
|
601 assert(NumNodes >= Itr->second.size());
|
|
120
|
602 NumNodes -= Itr->second.size();
|
|
|
603
|
|
|
604 Itr->second.clear();
|
|
|
605 }
|
|
|
606 }
|
|
|
607
|
|
|
608 /// Clears map from all contents.
|
|
|
609 void clear() {
|
|
|
610 MapVector<ValueType, SUList>::clear();
|
|
|
611 NumNodes = 0;
|
|
|
612 }
|
|
|
613
|
|
|
614 unsigned inline size() const { return NumNodes; }
|
|
|
615
|
|
121
|
616 /// Counts the number of SUs in this map after a reduction.
|
|
|
617 void reComputeSize() {
|
|
120
|
618 NumNodes = 0;
|
|
|
619 for (auto &I : *this)
|
|
|
620 NumNodes += I.second.size();
|
|
|
621 }
|
|
100
|
622
|
|
120
|
623 unsigned inline getTrueMemOrderLatency() const {
|
|
|
624 return TrueMemOrderLatency;
|
|
|
625 }
|
|
|
626
|
|
|
627 void dump();
|
|
|
628 };
|
|
|
629
|
|
|
630 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
|
|
|
631 Value2SUsMap &Val2SUsMap) {
|
|
|
632 for (auto &I : Val2SUsMap)
|
|
|
633 addChainDependencies(SU, I.second,
|
|
|
634 Val2SUsMap.getTrueMemOrderLatency());
|
|
|
635 }
|
|
|
636
|
|
|
637 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
|
|
|
638 Value2SUsMap &Val2SUsMap,
|
|
|
639 ValueType V) {
|
|
|
640 Value2SUsMap::iterator Itr = Val2SUsMap.find(V);
|
|
|
641 if (Itr != Val2SUsMap.end())
|
|
|
642 addChainDependencies(SU, Itr->second,
|
|
|
643 Val2SUsMap.getTrueMemOrderLatency());
|
|
|
644 }
|
|
100
|
645
|
|
120
|
646 void ScheduleDAGInstrs::addBarrierChain(Value2SUsMap &map) {
|
|
121
|
647 assert(BarrierChain != nullptr);
|
|
120
|
648
|
|
|
649 for (auto &I : map) {
|
|
|
650 SUList &sus = I.second;
|
|
|
651 for (auto *SU : sus)
|
|
|
652 SU->addPredBarrier(BarrierChain);
|
|
|
653 }
|
|
|
654 map.clear();
|
|
|
655 }
|
|
|
656
|
|
|
657 void ScheduleDAGInstrs::insertBarrierChain(Value2SUsMap &map) {
|
|
121
|
658 assert(BarrierChain != nullptr);
|
|
120
|
659
|
|
|
660 // Go through all lists of SUs.
|
|
|
661 for (Value2SUsMap::iterator I = map.begin(), EE = map.end(); I != EE;) {
|
|
|
662 Value2SUsMap::iterator CurrItr = I++;
|
|
|
663 SUList &sus = CurrItr->second;
|
|
|
664 SUList::iterator SUItr = sus.begin(), SUEE = sus.end();
|
|
|
665 for (; SUItr != SUEE; ++SUItr) {
|
|
|
666 // Stop on BarrierChain or any instruction above it.
|
|
|
667 if ((*SUItr)->NodeNum <= BarrierChain->NodeNum)
|
|
|
668 break;
|
|
|
669
|
|
|
670 (*SUItr)->addPredBarrier(BarrierChain);
|
|
100
|
671 }
|
|
|
672
|
|
120
|
673 // Remove also the BarrierChain from list if present.
|
|
|
674 if (SUItr != SUEE && *SUItr == BarrierChain)
|
|
|
675 SUItr++;
|
|
|
676
|
|
|
677 // Remove all SUs that are now successors of BarrierChain.
|
|
|
678 if (SUItr != sus.begin())
|
|
|
679 sus.erase(sus.begin(), SUItr);
|
|
100
|
680 }
|
|
120
|
681
|
|
|
682 // Remove all entries with empty su lists.
|
|
|
683 map.remove_if([&](std::pair<ValueType, SUList> &mapEntry) {
|
|
|
684 return (mapEntry.second.empty()); });
|
|
|
685
|
|
|
686 // Recompute the size of the map (NumNodes).
|
|
|
687 map.reComputeSize();
|
|
100
|
688 }
|
|
|
689
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
690 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
691 RegPressureTracker *RPTracker,
|
|
100
|
692 PressureDiffs *PDiffs,
|
|
|
693 LiveIntervals *LIS,
|
|
|
694 bool TrackLaneMasks) {
|
|
83
|
695 const TargetSubtargetInfo &ST = MF.getSubtarget();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
696 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
697 : ST.useAA();
|
|
120
|
698 AAForDep = UseAA ? AA : nullptr;
|
|
|
699
|
|
|
700 BarrierChain = nullptr;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
701
|
|
100
|
702 this->TrackLaneMasks = TrackLaneMasks;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
703 MISUnitMap.clear();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
704 ScheduleDAG::clearDAG();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
705
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
706 // Create an SUnit for each real instruction.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
707 initSUnits();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
708
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
709 if (PDiffs)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
710 PDiffs->init(SUnits.size());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
711
|
|
120
|
712 // We build scheduling units by walking a block's instruction list
|
|
|
713 // from bottom to top.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
714
|
|
120
|
715 // Each MIs' memory operand(s) is analyzed to a list of underlying
|
|
|
716 // objects. The SU is then inserted in the SUList(s) mapped from the
|
|
|
717 // Value(s). Each Value thus gets mapped to lists of SUs depending
|
|
|
718 // on it, stores and loads kept separately. Two SUs are trivially
|
|
|
719 // non-aliasing if they both depend on only identified Values and do
|
|
|
720 // not share any common Value.
|
|
|
721 Value2SUsMap Stores, Loads(1 /*TrueMemOrderLatency*/);
|
|
|
722
|
|
|
723 // Certain memory accesses are known to not alias any SU in Stores
|
|
|
724 // or Loads, and have therefore their own 'NonAlias'
|
|
|
725 // domain. E.g. spill / reload instructions never alias LLVM I/R
|
|
|
726 // Values. It would be nice to assume that this type of memory
|
|
|
727 // accesses always have a proper memory operand modelling, and are
|
|
|
728 // therefore never unanalyzable, but this is conservatively not
|
|
|
729 // done.
|
|
|
730 Value2SUsMap NonAliasStores, NonAliasLoads(1 /*TrueMemOrderLatency*/);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
731
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
732 // Remove any stale debug info; sometimes BuildSchedGraph is called again
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
733 // without emitting the info from the previous call.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
734 DbgValues.clear();
|
|
77
|
735 FirstDbgValue = nullptr;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
736
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
737 assert(Defs.empty() && Uses.empty() &&
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
738 "Only BuildGraph should update Defs/Uses");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
739 Defs.setUniverse(TRI->getNumRegs());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
740 Uses.setUniverse(TRI->getNumRegs());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
741
|
|
100
|
742 assert(CurrentVRegDefs.empty() && "nobody else should use CurrentVRegDefs");
|
|
|
743 assert(CurrentVRegUses.empty() && "nobody else should use CurrentVRegUses");
|
|
|
744 unsigned NumVirtRegs = MRI.getNumVirtRegs();
|
|
|
745 CurrentVRegDefs.setUniverse(NumVirtRegs);
|
|
|
746 CurrentVRegUses.setUniverse(NumVirtRegs);
|
|
|
747
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
748 // Model data dependencies between instructions being scheduled and the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
749 // ExitSU.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
750 addSchedBarrierDeps();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
751
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
752 // Walk the list of instructions, from bottom moving up.
|
|
77
|
753 MachineInstr *DbgMI = nullptr;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
754 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
755 MII != MIE; --MII) {
|
|
120
|
756 MachineInstr &MI = *std::prev(MII);
|
|
|
757 if (DbgMI) {
|
|
|
758 DbgValues.push_back(std::make_pair(DbgMI, &MI));
|
|
77
|
759 DbgMI = nullptr;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
760 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
761
|
|
120
|
762 if (MI.isDebugValue()) {
|
|
|
763 DbgMI = &MI;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
764 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
765 }
|
|
120
|
766 SUnit *SU = MISUnitMap[&MI];
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
767 assert(SU && "No SUnit mapped to this MI");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
768
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
769 if (RPTracker) {
|
|
100
|
770 RegisterOperands RegOpers;
|
|
120
|
771 RegOpers.collect(MI, *TRI, MRI, TrackLaneMasks, false);
|
|
100
|
772 if (TrackLaneMasks) {
|
|
|
773 SlotIndex SlotIdx = LIS->getInstructionIndex(MI);
|
|
|
774 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx);
|
|
|
775 }
|
|
|
776 if (PDiffs != nullptr)
|
|
|
777 PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI);
|
|
|
778
|
|
134
|
779 if (RPTracker->getPos() == RegionEnd || &*RPTracker->getPos() != &MI)
|
|
|
780 RPTracker->recedeSkipDebugValues();
|
|
120
|
781 assert(&*RPTracker->getPos() == &MI && "RPTracker in sync");
|
|
100
|
782 RPTracker->recede(RegOpers);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
783 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
784
|
|
77
|
785 assert(
|
|
120
|
786 (CanHandleTerminators || (!MI.isTerminator() && !MI.isPosition())) &&
|
|
77
|
787 "Cannot schedule terminators or labels!");
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
788
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
789 // Add register-based dependencies (data, anti, and output).
|
|
120
|
790 // For some instructions (calls, returns, inline-asm, etc.) there can
|
|
|
791 // be explicit uses and implicit defs, in which case the use will appear
|
|
|
792 // on the operand list before the def. Do two passes over the operand
|
|
|
793 // list to make sure that defs are processed before any uses.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
794 bool HasVRegDef = false;
|
|
120
|
795 for (unsigned j = 0, n = MI.getNumOperands(); j != n; ++j) {
|
|
|
796 const MachineOperand &MO = MI.getOperand(j);
|
|
|
797 if (!MO.isReg() || !MO.isDef())
|
|
|
798 continue;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
799 unsigned Reg = MO.getReg();
|
|
120
|
800 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
801 addPhysRegDeps(SU, j);
|
|
120
|
802 } else if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
|
803 HasVRegDef = true;
|
|
|
804 addVRegDefDeps(SU, j);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
805 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
806 }
|
|
120
|
807 // Now process all uses.
|
|
|
808 for (unsigned j = 0, n = MI.getNumOperands(); j != n; ++j) {
|
|
|
809 const MachineOperand &MO = MI.getOperand(j);
|
|
|
810 // Only look at use operands.
|
|
|
811 // We do not need to check for MO.readsReg() here because subsequent
|
|
|
812 // subregister defs will get output dependence edges and need no
|
|
|
813 // additional use dependencies.
|
|
|
814 if (!MO.isReg() || !MO.isUse())
|
|
|
815 continue;
|
|
|
816 unsigned Reg = MO.getReg();
|
|
|
817 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
|
818 addPhysRegDeps(SU, j);
|
|
|
819 } else if (TargetRegisterInfo::isVirtualRegister(Reg) && MO.readsReg()) {
|
|
|
820 addVRegUseDeps(SU, j);
|
|
|
821 }
|
|
|
822 }
|
|
|
823
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
824 // If we haven't seen any uses in this scheduling region, create a
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
825 // dependence edge to ExitSU to model the live-out latency. This is required
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
826 // for vreg defs with no in-region use, and prefetches with no vreg def.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
827 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
828 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
829 // check currently relies on being called before adding chain deps.
|
|
120
|
830 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
831 SDep Dep(SU, SDep::Artificial);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
832 Dep.setLatency(SU->Latency - 1);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
833 ExitSU.addPred(Dep);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
834 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
835
|
|
120
|
836 // Add memory dependencies (Note: isStoreToStackSlot and
|
|
|
837 // isLoadFromStackSLot are not usable after stack slots are lowered to
|
|
|
838 // actual addresses).
|
|
|
839
|
|
|
840 // This is a barrier event that acts as a pivotal node in the DAG.
|
|
|
841 if (isGlobalMemoryObject(AA, &MI)) {
|
|
|
842
|
|
|
843 // Become the barrier chain.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
844 if (BarrierChain)
|
|
120
|
845 BarrierChain->addPredBarrier(SU);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
846 BarrierChain = SU;
|
|
120
|
847
|
|
|
848 DEBUG(dbgs() << "Global memory object and new barrier chain: SU("
|
|
|
849 << BarrierChain->NodeNum << ").\n";);
|
|
|
850
|
|
|
851 // Add dependencies against everything below it and clear maps.
|
|
|
852 addBarrierChain(Stores);
|
|
|
853 addBarrierChain(Loads);
|
|
|
854 addBarrierChain(NonAliasStores);
|
|
|
855 addBarrierChain(NonAliasLoads);
|
|
|
856
|
|
|
857 continue;
|
|
|
858 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
859
|
|
120
|
860 // If it's not a store or a variant load, we're done.
|
|
|
861 if (!MI.mayStore() &&
|
|
|
862 !(MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA)))
|
|
|
863 continue;
|
|
|
864
|
|
|
865 // Always add dependecy edge to BarrierChain if present.
|
|
|
866 if (BarrierChain)
|
|
|
867 BarrierChain->addPredBarrier(SU);
|
|
83
|
868
|
|
120
|
869 // Find the underlying objects for MI. The Objs vector is either
|
|
|
870 // empty, or filled with the Values of memory locations which this
|
|
121
|
871 // SU depends on.
|
|
120
|
872 UnderlyingObjectsVector Objs;
|
|
121
|
873 bool ObjsFound = getUnderlyingObjectsForInstr(&MI, MFI, Objs,
|
|
|
874 MF.getDataLayout());
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
875
|
|
120
|
876 if (MI.mayStore()) {
|
|
121
|
877 if (!ObjsFound) {
|
|
120
|
878 // An unknown store depends on all stores and loads.
|
|
|
879 addChainDependencies(SU, Stores);
|
|
|
880 addChainDependencies(SU, NonAliasStores);
|
|
|
881 addChainDependencies(SU, Loads);
|
|
|
882 addChainDependencies(SU, NonAliasLoads);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
883
|
|
120
|
884 // Map this store to 'UnknownValue'.
|
|
|
885 Stores.insert(SU, UnknownValue);
|
|
|
886 } else {
|
|
|
887 // Add precise dependencies against all previously seen memory
|
|
|
888 // accesses mapped to the same Value(s).
|
|
|
889 for (const UnderlyingObject &UnderlObj : Objs) {
|
|
|
890 ValueType V = UnderlObj.getValue();
|
|
|
891 bool ThisMayAlias = UnderlObj.mayAlias();
|
|
77
|
892
|
|
120
|
893 // Add dependencies to previous stores and loads mapped to V.
|
|
|
894 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
|
|
|
895 addChainDependencies(SU, (ThisMayAlias ? Loads : NonAliasLoads), V);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
896 }
|
|
120
|
897 // Update the store map after all chains have been added to avoid adding
|
|
|
898 // self-loop edge if multiple underlying objects are present.
|
|
|
899 for (const UnderlyingObject &UnderlObj : Objs) {
|
|
|
900 ValueType V = UnderlObj.getValue();
|
|
|
901 bool ThisMayAlias = UnderlObj.mayAlias();
|
|
|
902
|
|
|
903 // Map this store to V.
|
|
|
904 (ThisMayAlias ? Stores : NonAliasStores).insert(SU, V);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
905 }
|
|
120
|
906 // The store may have dependencies to unanalyzable loads and
|
|
|
907 // stores.
|
|
|
908 addChainDependencies(SU, Loads, UnknownValue);
|
|
|
909 addChainDependencies(SU, Stores, UnknownValue);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
910 }
|
|
120
|
911 } else { // SU is a load.
|
|
121
|
912 if (!ObjsFound) {
|
|
120
|
913 // An unknown load depends on all stores.
|
|
|
914 addChainDependencies(SU, Stores);
|
|
|
915 addChainDependencies(SU, NonAliasStores);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
916
|
|
120
|
917 Loads.insert(SU, UnknownValue);
|
|
|
918 } else {
|
|
|
919 for (const UnderlyingObject &UnderlObj : Objs) {
|
|
|
920 ValueType V = UnderlObj.getValue();
|
|
|
921 bool ThisMayAlias = UnderlObj.mayAlias();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
922
|
|
120
|
923 // Add precise dependencies against all previously seen stores
|
|
|
924 // mapping to the same Value(s).
|
|
|
925 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
|
|
|
926
|
|
|
927 // Map this load to V.
|
|
|
928 (ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
929 }
|
|
120
|
930 // The load may have dependencies to unanalyzable stores.
|
|
|
931 addChainDependencies(SU, Stores, UnknownValue);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
932 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
933 }
|
|
120
|
934
|
|
|
935 // Reduce maps if they grow huge.
|
|
|
936 if (Stores.size() + Loads.size() >= HugeRegion) {
|
|
|
937 DEBUG(dbgs() << "Reducing Stores and Loads maps.\n";);
|
|
|
938 reduceHugeMemNodeMaps(Stores, Loads, getReductionSize());
|
|
|
939 }
|
|
|
940 if (NonAliasStores.size() + NonAliasLoads.size() >= HugeRegion) {
|
|
|
941 DEBUG(dbgs() << "Reducing NonAliasStores and NonAliasLoads maps.\n";);
|
|
|
942 reduceHugeMemNodeMaps(NonAliasStores, NonAliasLoads, getReductionSize());
|
|
|
943 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
944 }
|
|
120
|
945
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
946 if (DbgMI)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
947 FirstDbgValue = DbgMI;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
948
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
949 Defs.clear();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
950 Uses.clear();
|
|
100
|
951 CurrentVRegDefs.clear();
|
|
|
952 CurrentVRegUses.clear();
|
|
120
|
953 }
|
|
|
954
|
|
|
955 raw_ostream &llvm::operator<<(raw_ostream &OS, const PseudoSourceValue* PSV) {
|
|
|
956 PSV->printCustom(OS);
|
|
|
957 return OS;
|
|
|
958 }
|
|
|
959
|
|
|
960 void ScheduleDAGInstrs::Value2SUsMap::dump() {
|
|
|
961 for (auto &Itr : *this) {
|
|
|
962 if (Itr.first.is<const Value*>()) {
|
|
|
963 const Value *V = Itr.first.get<const Value*>();
|
|
|
964 if (isa<UndefValue>(V))
|
|
|
965 dbgs() << "Unknown";
|
|
|
966 else
|
|
|
967 V->printAsOperand(dbgs());
|
|
|
968 }
|
|
|
969 else if (Itr.first.is<const PseudoSourceValue*>())
|
|
|
970 dbgs() << Itr.first.get<const PseudoSourceValue*>();
|
|
|
971 else
|
|
|
972 llvm_unreachable("Unknown Value type.");
|
|
|
973
|
|
|
974 dbgs() << " : ";
|
|
|
975 dumpSUList(Itr.second);
|
|
|
976 }
|
|
|
977 }
|
|
|
978
|
|
|
979 void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores,
|
|
|
980 Value2SUsMap &loads, unsigned N) {
|
|
|
981 DEBUG(dbgs() << "Before reduction:\nStoring SUnits:\n";
|
|
|
982 stores.dump();
|
|
|
983 dbgs() << "Loading SUnits:\n";
|
|
|
984 loads.dump());
|
|
|
985
|
|
|
986 // Insert all SU's NodeNums into a vector and sort it.
|
|
|
987 std::vector<unsigned> NodeNums;
|
|
|
988 NodeNums.reserve(stores.size() + loads.size());
|
|
|
989 for (auto &I : stores)
|
|
|
990 for (auto *SU : I.second)
|
|
|
991 NodeNums.push_back(SU->NodeNum);
|
|
|
992 for (auto &I : loads)
|
|
|
993 for (auto *SU : I.second)
|
|
|
994 NodeNums.push_back(SU->NodeNum);
|
|
|
995 std::sort(NodeNums.begin(), NodeNums.end());
|
|
|
996
|
|
|
997 // The N last elements in NodeNums will be removed, and the SU with
|
|
|
998 // the lowest NodeNum of them will become the new BarrierChain to
|
|
|
999 // let the not yet seen SUs have a dependency to the removed SUs.
|
|
121
|
1000 assert(N <= NodeNums.size());
|
|
120
|
1001 SUnit *newBarrierChain = &SUnits[*(NodeNums.end() - N)];
|
|
|
1002 if (BarrierChain) {
|
|
|
1003 // The aliasing and non-aliasing maps reduce independently of each
|
|
|
1004 // other, but share a common BarrierChain. Check if the
|
|
|
1005 // newBarrierChain is above the former one. If it is not, it may
|
|
|
1006 // introduce a loop to use newBarrierChain, so keep the old one.
|
|
|
1007 if (newBarrierChain->NodeNum < BarrierChain->NodeNum) {
|
|
|
1008 BarrierChain->addPredBarrier(newBarrierChain);
|
|
|
1009 BarrierChain = newBarrierChain;
|
|
|
1010 DEBUG(dbgs() << "Inserting new barrier chain: SU("
|
|
|
1011 << BarrierChain->NodeNum << ").\n";);
|
|
|
1012 }
|
|
|
1013 else
|
|
|
1014 DEBUG(dbgs() << "Keeping old barrier chain: SU("
|
|
|
1015 << BarrierChain->NodeNum << ").\n";);
|
|
|
1016 }
|
|
|
1017 else
|
|
|
1018 BarrierChain = newBarrierChain;
|
|
|
1019
|
|
|
1020 insertBarrierChain(stores);
|
|
|
1021 insertBarrierChain(loads);
|
|
|
1022
|
|
|
1023 DEBUG(dbgs() << "After reduction:\nStoring SUnits:\n";
|
|
|
1024 stores.dump();
|
|
|
1025 dbgs() << "Loading SUnits:\n";
|
|
|
1026 loads.dump());
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1027 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1028
|
|
121
|
1029 static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs,
|
|
|
1030 MachineInstr &MI, bool addToLiveRegs) {
|
|
|
1031 for (MachineOperand &MO : MI.operands()) {
|
|
|
1032 if (!MO.isReg() || !MO.readsReg())
|
|
|
1033 continue;
|
|
|
1034 unsigned Reg = MO.getReg();
|
|
|
1035 if (!Reg)
|
|
|
1036 continue;
|
|
77
|
1037
|
|
121
|
1038 // Things that are available after the instruction are killed by it.
|
|
|
1039 bool IsKill = LiveRegs.available(MRI, Reg);
|
|
|
1040 MO.setIsKill(IsKill);
|
|
|
1041 if (addToLiveRegs)
|
|
|
1042 LiveRegs.addReg(Reg);
|
|
95
|
1043 }
|
|
|
1044 }
|
|
|
1045
|
|
121
|
1046 void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
|
|
134
|
1047 DEBUG(dbgs() << "Fixup kills for " << printMBBReference(MBB) << '\n');
|
|
77
|
1048
|
|
121
|
1049 LiveRegs.init(*TRI);
|
|
|
1050 LiveRegs.addLiveOuts(MBB);
|
|
77
|
1051
|
|
|
1052 // Examine block from end to start...
|
|
121
|
1053 for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
|
|
120
|
1054 if (MI.isDebugValue())
|
|
77
|
1055 continue;
|
|
|
1056
|
|
|
1057 // Update liveness. Registers that are defed but not used in this
|
|
|
1058 // instruction are now dead. Mark register and all subregs as they
|
|
|
1059 // are completely defined.
|
|
121
|
1060 for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
|
|
|
1061 const MachineOperand &MO = *O;
|
|
|
1062 if (MO.isReg()) {
|
|
|
1063 if (!MO.isDef())
|
|
|
1064 continue;
|
|
|
1065 unsigned Reg = MO.getReg();
|
|
|
1066 if (!Reg)
|
|
|
1067 continue;
|
|
|
1068 LiveRegs.removeReg(Reg);
|
|
|
1069 } else if (MO.isRegMask()) {
|
|
|
1070 LiveRegs.removeRegsInMask(MO);
|
|
|
1071 }
|
|
77
|
1072 }
|
|
|
1073
|
|
121
|
1074 // If there is a bundle header fix it up first.
|
|
|
1075 if (!MI.isBundled()) {
|
|
|
1076 toggleKills(MRI, LiveRegs, MI, true);
|
|
|
1077 } else {
|
|
|
1078 MachineBasicBlock::instr_iterator First = MI.getIterator();
|
|
|
1079 if (MI.isBundle()) {
|
|
|
1080 toggleKills(MRI, LiveRegs, MI, false);
|
|
|
1081 ++First;
|
|
77
|
1082 }
|
|
121
|
1083 // Some targets make the (questionable) assumtion that the instructions
|
|
|
1084 // inside the bundle are ordered and consequently only the last use of
|
|
|
1085 // a register inside the bundle can kill it.
|
|
|
1086 MachineBasicBlock::instr_iterator I = std::next(First);
|
|
|
1087 while (I->isBundledWithSucc())
|
|
|
1088 ++I;
|
|
|
1089 do {
|
|
|
1090 if (!I->isDebugValue())
|
|
|
1091 toggleKills(MRI, LiveRegs, *I, true);
|
|
|
1092 --I;
|
|
|
1093 } while(I != First);
|
|
77
|
1094 }
|
|
|
1095 }
|
|
|
1096 }
|
|
|
1097
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1098 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
|
|
121
|
1099 // Cannot completely remove virtual function even in release mode.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1100 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1101 SU->getInstr()->dump();
|
|
134
|
1102 dbgs() << '\n';
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1103 #endif
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1104 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1105
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1106 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1107 std::string s;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1108 raw_string_ostream oss(s);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1109 if (SU == &EntrySU)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1110 oss << "<entry>";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1111 else if (SU == &ExitSU)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1112 oss << "<exit>";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1113 else
|
|
95
|
1114 SU->getInstr()->print(oss, /*SkipOpers=*/true);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1115 return oss.str();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1116 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1117
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1118 /// Return the basic block label. It is not necessarilly unique because a block
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1119 /// contains multiple scheduling regions. But it is fine for visualization.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1120 std::string ScheduleDAGInstrs::getDAGName() const {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1121 return "dag." + BB->getFullName();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1122 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1123
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1124 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1125 // SchedDFSResult Implementation
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1126 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1127
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1128 namespace llvm {
|
|
121
|
1129
|
|
|
1130 /// Internal state used to compute SchedDFSResult.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1131 class SchedDFSImpl {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1132 SchedDFSResult &R;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1133
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1134 /// Join DAG nodes into equivalence classes by their subtree.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1135 IntEqClasses SubtreeClasses;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1136 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
|
|
121
|
1137 std::vector<std::pair<const SUnit *, const SUnit*>> ConnectionPairs;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1138
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1139 struct RootData {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1140 unsigned NodeID;
|
|
121
|
1141 unsigned ParentNodeID; ///< Parent node (member of the parent subtree).
|
|
|
1142 unsigned SubInstrCount = 0; ///< Instr count in this tree only, not
|
|
|
1143 /// children.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1144
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1145 RootData(unsigned id): NodeID(id),
|
|
121
|
1146 ParentNodeID(SchedDFSResult::InvalidSubtreeID) {}
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1147
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1148 unsigned getSparseSetIndex() const { return NodeID; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1149 };
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1150
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1151 SparseSet<RootData> RootSet;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1152
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1153 public:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1154 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1155 RootSet.setUniverse(R.DFSNodeData.size());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1156 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1157
|
|
121
|
1158 /// Returns true if this node been visited by the DFS traversal.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1159 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1160 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1161 /// ID. Later, SubtreeID is updated but remains valid.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1162 bool isVisited(const SUnit *SU) const {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1163 return R.DFSNodeData[SU->NodeNum].SubtreeID
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1164 != SchedDFSResult::InvalidSubtreeID;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1165 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1166
|
|
121
|
1167 /// Initializes this node's instruction count. We don't need to flag the node
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1168 /// visited until visitPostorder because the DAG cannot have cycles.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1169 void visitPreorder(const SUnit *SU) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1170 R.DFSNodeData[SU->NodeNum].InstrCount =
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1171 SU->getInstr()->isTransient() ? 0 : 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1172 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1173
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1174 /// Called once for each node after all predecessors are visited. Revisit this
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1175 /// node's predecessors and potentially join them now that we know the ILP of
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1176 /// the other predecessors.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1177 void visitPostorderNode(const SUnit *SU) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1178 // Mark this node as the root of a subtree. It may be joined with its
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1179 // successors later.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1180 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1181 RootData RData(SU->NodeNum);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1182 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1183
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1184 // If any predecessors are still in their own subtree, they either cannot be
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1185 // joined or are large enough to remain separate. If this parent node's
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1186 // total instruction count is not greater than a child subtree by at least
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1187 // the subtree limit, then try to join it now since splitting subtrees is
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1188 // only useful if multiple high-pressure paths are possible.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1189 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
|
|
120
|
1190 for (const SDep &PredDep : SU->Preds) {
|
|
|
1191 if (PredDep.getKind() != SDep::Data)
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1192 continue;
|
|
120
|
1193 unsigned PredNum = PredDep.getSUnit()->NodeNum;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1194 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
|
|
120
|
1195 joinPredSubtree(PredDep, SU, /*CheckLimit=*/false);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1196
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1197 // Either link or merge the TreeData entry from the child to the parent.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1198 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1199 // If the predecessor's parent is invalid, this is a tree edge and the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1200 // current node is the parent.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1201 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1202 RootSet[PredNum].ParentNodeID = SU->NodeNum;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1203 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1204 else if (RootSet.count(PredNum)) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1205 // The predecessor is not a root, but is still in the root set. This
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1206 // must be the new parent that it was just joined to. Note that
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1207 // RootSet[PredNum].ParentNodeID may either be invalid or may still be
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1208 // set to the original parent.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1209 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1210 RootSet.erase(PredNum);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1211 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1212 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1213 RootSet[SU->NodeNum] = RData;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1214 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1215
|
|
121
|
1216 /// \brief Called once for each tree edge after calling visitPostOrderNode on
|
|
|
1217 /// the predecessor. Increment the parent node's instruction count and
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1218 /// preemptively join this subtree to its parent's if it is small enough.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1219 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1220 R.DFSNodeData[Succ->NodeNum].InstrCount
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1221 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1222 joinPredSubtree(PredDep, Succ);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1223 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1224
|
|
121
|
1225 /// Adds a connection for cross edges.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1226 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1227 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1228 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1229
|
|
121
|
1230 /// Sets each node's subtree ID to the representative ID and record
|
|
|
1231 /// connections between trees.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1232 void finalize() {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1233 SubtreeClasses.compress();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1234 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1235 assert(SubtreeClasses.getNumClasses() == RootSet.size()
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1236 && "number of roots should match trees");
|
|
120
|
1237 for (const RootData &Root : RootSet) {
|
|
|
1238 unsigned TreeID = SubtreeClasses[Root.NodeID];
|
|
|
1239 if (Root.ParentNodeID != SchedDFSResult::InvalidSubtreeID)
|
|
|
1240 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[Root.ParentNodeID];
|
|
|
1241 R.DFSTreeData[TreeID].SubInstrCount = Root.SubInstrCount;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1242 // Note that SubInstrCount may be greater than InstrCount if we joined
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1243 // subtrees across a cross edge. InstrCount will be attributed to the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1244 // original parent, while SubInstrCount will be attributed to the joined
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1245 // parent.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1246 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1247 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1248 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1249 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1250 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1251 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1252 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1253 << R.DFSNodeData[Idx].SubtreeID << '\n');
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1254 }
|
|
120
|
1255 for (const std::pair<const SUnit*, const SUnit*> &P : ConnectionPairs) {
|
|
|
1256 unsigned PredTree = SubtreeClasses[P.first->NodeNum];
|
|
|
1257 unsigned SuccTree = SubtreeClasses[P.second->NodeNum];
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1258 if (PredTree == SuccTree)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1259 continue;
|
|
120
|
1260 unsigned Depth = P.first->getDepth();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1261 addConnection(PredTree, SuccTree, Depth);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1262 addConnection(SuccTree, PredTree, Depth);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1263 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1264 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1265
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1266 protected:
|
|
121
|
1267 /// Joins the predecessor subtree with the successor that is its DFS parent.
|
|
|
1268 /// Applies some heuristics before joining.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1269 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1270 bool CheckLimit = true) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1271 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1272
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1273 // Check if the predecessor is already joined.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1274 const SUnit *PredSU = PredDep.getSUnit();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1275 unsigned PredNum = PredSU->NodeNum;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1276 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1277 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1278
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1279 // Four is the magic number of successors before a node is considered a
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1280 // pinch point.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1281 unsigned NumDataSucs = 0;
|
|
120
|
1282 for (const SDep &SuccDep : PredSU->Succs) {
|
|
|
1283 if (SuccDep.getKind() == SDep::Data) {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1284 if (++NumDataSucs >= 4)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1285 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1286 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1287 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1288 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1289 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1290 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1291 SubtreeClasses.join(Succ->NodeNum, PredNum);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1292 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1293 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1294
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1295 /// Called by finalize() to record a connection between trees.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1296 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1297 if (!Depth)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1298 return;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1299
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1300 do {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1301 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1302 R.SubtreeConnections[FromTree];
|
|
120
|
1303 for (SchedDFSResult::Connection &C : Connections) {
|
|
|
1304 if (C.TreeID == ToTree) {
|
|
|
1305 C.Level = std::max(C.Level, Depth);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1306 return;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1307 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1308 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1309 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1310 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1311 } while (FromTree != SchedDFSResult::InvalidSubtreeID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1312 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1313 };
|
|
121
|
1314
|
|
|
1315 } // end namespace llvm
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1316
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1317 namespace {
|
|
121
|
1318
|
|
|
1319 /// Manage the stack used by a reverse depth-first search over the DAG.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1320 class SchedDAGReverseDFS {
|
|
121
|
1321 std::vector<std::pair<const SUnit *, SUnit::const_pred_iterator>> DFSStack;
|
|
|
1322
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1323 public:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1324 bool isComplete() const { return DFSStack.empty(); }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1325
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1326 void follow(const SUnit *SU) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1327 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1328 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1329 void advance() { ++DFSStack.back().second; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1330
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1331 const SDep *backtrack() {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1332 DFSStack.pop_back();
|
|
77
|
1333 return DFSStack.empty() ? nullptr : std::prev(DFSStack.back().second);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1334 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1335
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1336 const SUnit *getCurr() const { return DFSStack.back().first; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1337
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1338 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1339
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1340 SUnit::const_pred_iterator getPredEnd() const {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1341 return getCurr()->Preds.end();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1342 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1343 };
|
|
121
|
1344
|
|
|
1345 } // end anonymous namespace
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1346
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1347 static bool hasDataSucc(const SUnit *SU) {
|
|
120
|
1348 for (const SDep &SuccDep : SU->Succs) {
|
|
|
1349 if (SuccDep.getKind() == SDep::Data &&
|
|
|
1350 !SuccDep.getSUnit()->isBoundaryNode())
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1351 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1352 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1353 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1354 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1355
|
|
121
|
1356 /// Computes an ILP metric for all nodes in the subDAG reachable via depth-first
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1357 /// search from this root.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1358 void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1359 if (!IsBottomUp)
|
|
121
|
1360 llvm_unreachable("Top-down ILP metric is unimplemented");
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1361
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1362 SchedDFSImpl Impl(*this);
|
|
120
|
1363 for (const SUnit &SU : SUnits) {
|
|
|
1364 if (Impl.isVisited(&SU) || hasDataSucc(&SU))
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1365 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1366
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1367 SchedDAGReverseDFS DFS;
|
|
120
|
1368 Impl.visitPreorder(&SU);
|
|
|
1369 DFS.follow(&SU);
|
|
121
|
1370 while (true) {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1371 // Traverse the leftmost path as far as possible.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1372 while (DFS.getPred() != DFS.getPredEnd()) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1373 const SDep &PredDep = *DFS.getPred();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1374 DFS.advance();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1375 // Ignore non-data edges.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1376 if (PredDep.getKind() != SDep::Data
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1377 || PredDep.getSUnit()->isBoundaryNode()) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1378 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1379 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1380 // An already visited edge is a cross edge, assuming an acyclic DAG.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1381 if (Impl.isVisited(PredDep.getSUnit())) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1382 Impl.visitCrossEdge(PredDep, DFS.getCurr());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1383 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1384 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1385 Impl.visitPreorder(PredDep.getSUnit());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1386 DFS.follow(PredDep.getSUnit());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1387 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1388 // Visit the top of the stack in postorder and backtrack.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1389 const SUnit *Child = DFS.getCurr();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1390 const SDep *PredDep = DFS.backtrack();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1391 Impl.visitPostorderNode(Child);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1392 if (PredDep)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1393 Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1394 if (DFS.isComplete())
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1395 break;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1396 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1397 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1398 Impl.finalize();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1399 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1400
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1401 /// The root of the given SubtreeID was just scheduled. For all subtrees
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1402 /// connected to this tree, record the depth of the connection so that the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1403 /// nearest connected subtrees can be prioritized.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1404 void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
|
|
120
|
1405 for (const Connection &C : SubtreeConnections[SubtreeID]) {
|
|
|
1406 SubtreeConnectLevels[C.TreeID] =
|
|
|
1407 std::max(SubtreeConnectLevels[C.TreeID], C.Level);
|
|
|
1408 DEBUG(dbgs() << " Tree: " << C.TreeID
|
|
|
1409 << " @" << SubtreeConnectLevels[C.TreeID] << '\n');
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1410 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1411 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1412
|
|
121
|
1413 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
|
|
1414 LLVM_DUMP_METHOD void ILPValue::print(raw_ostream &OS) const {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1415 OS << InstrCount << " / " << Length << " = ";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1416 if (!Length)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1417 OS << "BADILP";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1418 else
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1419 OS << format("%g", ((double)InstrCount / Length));
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1420 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1421
|
|
121
|
1422 LLVM_DUMP_METHOD void ILPValue::dump() const {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1423 dbgs() << *this << '\n';
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1424 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1425
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1426 namespace llvm {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1427
|
|
77
|
1428 LLVM_DUMP_METHOD
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1429 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1430 Val.print(OS);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1431 return OS;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1432 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1433
|
|
121
|
1434 } // end namespace llvm
|
|
|
1435
|
|
|
1436 #endif
|
