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1 //===- llvm/Target/TargetSchedule.cpp - Sched Machine Model ---------------===//
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2 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 // The LLVM Compiler Infrastructure
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 // This file is distributed under the University of Illinois Open Source
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6 // License. See LICENSE.TXT for details.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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7 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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8 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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9 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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10 // This file implements a wrapper around MCSchedModel that allows the interface
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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11 // to benefit from information currently only available in TargetInstrInfo.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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13 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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14
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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15 #include "llvm/CodeGen/TargetSchedule.h"
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121
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16 #include "llvm/CodeGen/MachineFunction.h"
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17 #include "llvm/CodeGen/MachineInstr.h"
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18 #include "llvm/CodeGen/MachineOperand.h"
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134
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19 #include "llvm/CodeGen/TargetInstrInfo.h"
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20 #include "llvm/CodeGen/TargetRegisterInfo.h"
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21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
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121
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22 #include "llvm/MC/MCInstrDesc.h"
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23 #include "llvm/MC/MCInstrItineraries.h"
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24 #include "llvm/MC/MCSchedule.h"
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25 #include "llvm/Support/CommandLine.h"
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121
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26 #include "llvm/Support/ErrorHandling.h"
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27 #include "llvm/Support/raw_ostream.h"
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121
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28 #include <algorithm>
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29 #include <cassert>
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30 #include <cstdint>
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31
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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32 using namespace llvm;
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33
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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34 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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35 cl::desc("Use TargetSchedModel for latency lookup"));
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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36
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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37 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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38 cl::desc("Use InstrItineraryData for latency lookup"));
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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39
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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40 bool TargetSchedModel::hasInstrSchedModel() const {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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41 return EnableSchedModel && SchedModel.hasInstrSchedModel();
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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42 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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43
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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44 bool TargetSchedModel::hasInstrItineraries() const {
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45 return EnableSchedItins && !InstrItins.isEmpty();
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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46 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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47
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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48 static unsigned gcd(unsigned Dividend, unsigned Divisor) {
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49 // Dividend and Divisor will be naturally swapped as needed.
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121
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50 while (Divisor) {
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51 unsigned Rem = Dividend % Divisor;
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52 Dividend = Divisor;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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53 Divisor = Rem;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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54 };
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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55 return Dividend;
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56 }
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121
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57
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58 static unsigned lcm(unsigned A, unsigned B) {
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59 unsigned LCM = (uint64_t(A) * B) / gcd(A, B);
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60 assert((LCM >= A && LCM >= B) && "LCM overflow");
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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61 return LCM;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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62 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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63
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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64 void TargetSchedModel::init(const MCSchedModel &sm,
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65 const TargetSubtargetInfo *sti,
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66 const TargetInstrInfo *tii) {
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67 SchedModel = sm;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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68 STI = sti;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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69 TII = tii;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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70 STI->initInstrItins(InstrItins);
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71
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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72 unsigned NumRes = SchedModel.getNumProcResourceKinds();
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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73 ResourceFactors.resize(NumRes);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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74 ResourceLCM = SchedModel.IssueWidth;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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75 for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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76 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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77 if (NumUnits > 0)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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78 ResourceLCM = lcm(ResourceLCM, NumUnits);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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79 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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80 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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81 for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
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82 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
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83 ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
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84 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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85 }
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86
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121
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87 /// Returns true only if instruction is specified as single issue.
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88 bool TargetSchedModel::mustBeginGroup(const MachineInstr *MI,
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89 const MCSchedClassDesc *SC) const {
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90 if (hasInstrSchedModel()) {
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91 if (!SC)
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92 SC = resolveSchedClass(MI);
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93 if (SC->isValid())
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94 return SC->BeginGroup;
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95 }
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96 return false;
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97 }
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98
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99 bool TargetSchedModel::mustEndGroup(const MachineInstr *MI,
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100 const MCSchedClassDesc *SC) const {
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101 if (hasInstrSchedModel()) {
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102 if (!SC)
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103 SC = resolveSchedClass(MI);
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104 if (SC->isValid())
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105 return SC->EndGroup;
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106 }
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107 return false;
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108 }
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109
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110 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI,
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111 const MCSchedClassDesc *SC) const {
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112 if (hasInstrItineraries()) {
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113 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
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120
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114 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI);
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115 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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116 if (hasInstrSchedModel()) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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117 if (!SC)
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118 SC = resolveSchedClass(MI);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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119 if (SC->isValid())
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120 return SC->NumMicroOps;
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121 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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122 return MI->isTransient() ? 0 : 1;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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123 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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124
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125 // The machine model may explicitly specify an invalid latency, which
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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126 // effectively means infinite latency. Since users of the TargetSchedule API
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127 // don't know how to handle this, we convert it to a very large latency that is
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128 // easy to distinguish when debugging the DAG but won't induce overflow.
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129 static unsigned capLatency(int Cycles) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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130 return Cycles >= 0 ? Cycles : 1000;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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131 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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132
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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133 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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134 /// evaluation of predicates that depend on instruction operands or flags.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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135 const MCSchedClassDesc *TargetSchedModel::
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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136 resolveSchedClass(const MachineInstr *MI) const {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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137 // Get the definition's scheduling class descriptor from this machine model.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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138 unsigned SchedClass = MI->getDesc().getSchedClass();
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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139 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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140 if (!SCDesc->isValid())
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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141 return SCDesc;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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142
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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143 #ifndef NDEBUG
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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144 unsigned NIter = 0;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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145 #endif
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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146 while (SCDesc->isVariant()) {
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147 assert(++NIter < 6 && "Variants are nested deeper than the magic number");
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148
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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149 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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150 SCDesc = SchedModel.getSchedClassDesc(SchedClass);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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151 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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152 return SCDesc;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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153 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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154
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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155 /// Find the def index of this operand. This index maps to the machine model and
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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156 /// is independent of use operands. Def operands may be reordered with uses or
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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157 /// merged with uses without affecting the def index (e.g. before/after
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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158 /// regalloc). However, an instruction's def operands must never be reordered
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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159 /// with respect to each other.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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160 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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161 unsigned DefIdx = 0;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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162 for (unsigned i = 0; i != DefOperIdx; ++i) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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163 const MachineOperand &MO = MI->getOperand(i);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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164 if (MO.isReg() && MO.isDef())
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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165 ++DefIdx;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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166 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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167 return DefIdx;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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168 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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169
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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170 /// Find the use index of this operand. This is independent of the instruction's
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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171 /// def operands.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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172 ///
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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173 /// Note that uses are not determined by the operand's isUse property, which
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
174 /// is simply the inverse of isDef. Here we consider any readsReg operand to be
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
175 /// a "use". The machine model allows an operand to be both a Def and Use.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
176 static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
177 unsigned UseIdx = 0;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
178 for (unsigned i = 0; i != UseOperIdx; ++i) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
179 const MachineOperand &MO = MI->getOperand(i);
|
|
120
|
180 if (MO.isReg() && MO.readsReg() && !MO.isDef())
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
181 ++UseIdx;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
182 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
183 return UseIdx;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
184 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
185
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
186 // Top-level API for clients that know the operand indices.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
187 unsigned TargetSchedModel::computeOperandLatency(
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
188 const MachineInstr *DefMI, unsigned DefOperIdx,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
189 const MachineInstr *UseMI, unsigned UseOperIdx) const {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
190
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
191 if (!hasInstrSchedModel() && !hasInstrItineraries())
|
|
120
|
192 return TII->defaultDefLatency(SchedModel, *DefMI);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
193
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
194 if (hasInstrItineraries()) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
195 int OperLatency = 0;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
196 if (UseMI) {
|
|
120
|
197 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
|
|
|
198 *UseMI, UseOperIdx);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
199 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
200 else {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
201 unsigned DefClass = DefMI->getDesc().getSchedClass();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
202 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
203 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
204 if (OperLatency >= 0)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
205 return OperLatency;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
206
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
207 // No operand latency was found.
|
|
120
|
208 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
209
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
210 // Expected latency is the max of the stage latency and itinerary props.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
211 // Rather than directly querying InstrItins stage latency, we call a TII
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
212 // hook to allow subtargets to specialize latency. This hook is only
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
213 // applicable to the InstrItins model. InstrSchedModel should model all
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
214 // special cases without TII hooks.
|
|
120
|
215 InstrLatency =
|
|
|
216 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
217 return InstrLatency;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
218 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
219 // hasInstrSchedModel()
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
220 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
221 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
222 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
223 // Lookup the definition's write latency in SubtargetInfo.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
224 const MCWriteLatencyEntry *WLEntry =
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
225 STI->getWriteLatencyEntry(SCDesc, DefIdx);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
226 unsigned WriteID = WLEntry->WriteResourceID;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
227 unsigned Latency = capLatency(WLEntry->Cycles);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
228 if (!UseMI)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
229 return Latency;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
230
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
231 // Lookup the use's latency adjustment in SubtargetInfo.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
232 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
233 if (UseDesc->NumReadAdvanceEntries == 0)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
234 return Latency;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
235 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
236 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
237 if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
238 return 0;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
239 return Latency - Advance;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
240 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
241 // If DefIdx does not exist in the model (e.g. implicit defs), then return
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
242 // unit latency (defaultDefLatency may be too conservative).
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
243 #ifndef NDEBUG
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
244 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
245 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
246 && SchedModel.isComplete()) {
|
|
95
|
247 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
|
|
100
|
248 << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";
|
|
95
|
249 llvm_unreachable("incomplete machine model");
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
250 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
251 #endif
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
252 // FIXME: Automatically giving all implicit defs defaultDefLatency is
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
253 // undesirable. We should only do it for defs that are known to the MC
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
254 // desc like flags. Truly implicit defs should get 1 cycle latency.
|
|
120
|
255 return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI);
|
|
77
|
256 }
|
|
|
257
|
|
95
|
258 unsigned
|
|
|
259 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const {
|
|
|
260 unsigned Latency = 0;
|
|
|
261 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
|
|
|
262 DefIdx != DefEnd; ++DefIdx) {
|
|
|
263 // Lookup the definition's write latency in SubtargetInfo.
|
|
|
264 const MCWriteLatencyEntry *WLEntry =
|
|
|
265 STI->getWriteLatencyEntry(&SCDesc, DefIdx);
|
|
|
266 Latency = std::max(Latency, capLatency(WLEntry->Cycles));
|
|
|
267 }
|
|
|
268 return Latency;
|
|
|
269 }
|
|
|
270
|
|
77
|
271 unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const {
|
|
|
272 assert(hasInstrSchedModel() && "Only call this function with a SchedModel");
|
|
|
273
|
|
|
274 unsigned SCIdx = TII->get(Opcode).getSchedClass();
|
|
|
275 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCIdx);
|
|
|
276
|
|
95
|
277 if (SCDesc->isValid() && !SCDesc->isVariant())
|
|
|
278 return computeInstrLatency(*SCDesc);
|
|
77
|
279
|
|
121
|
280 if (SCDesc->isValid()) {
|
|
|
281 assert (!SCDesc->isVariant() && "No MI sched latency: SCDesc->isVariant()");
|
|
|
282 return computeInstrLatency(*SCDesc);
|
|
|
283 }
|
|
|
284 return 0;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
285 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
286
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
287 unsigned
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
288 TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
289 bool UseDefaultDefLatency) const {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
290 // For the itinerary model, fall back to the old subtarget hook.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
291 // Allow subtargets to compute Bundle latencies outside the machine model.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
292 if (hasInstrItineraries() || MI->isBundle() ||
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
293 (!hasInstrSchedModel() && !UseDefaultDefLatency))
|
|
120
|
294 return TII->getInstrLatency(&InstrItins, *MI);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
295
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
296 if (hasInstrSchedModel()) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
297 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
|
|
95
|
298 if (SCDesc->isValid())
|
|
|
299 return computeInstrLatency(*SCDesc);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
300 }
|
|
120
|
301 return TII->defaultDefLatency(SchedModel, *MI);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
302 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
303
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
304 unsigned TargetSchedModel::
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
305 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
306 const MachineInstr *DepMI) const {
|
|
120
|
307 if (!SchedModel.isOutOfOrder())
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
308 return 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
309
|
|
120
|
310 // Out-of-order processor can dispatch WAW dependencies in the same cycle.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
311
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
312 // Treat predication as a data dependency for out-of-order cpus. In-order
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
313 // cpus do not need to treat predicated writes specially.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
314 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
315 // TODO: The following hack exists because predication passes do not
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
316 // correctly append imp-use operands, and readsReg() strangely returns false
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
317 // for predicated defs.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
318 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
|
|
121
|
319 const MachineFunction &MF = *DefMI->getMF();
|
|
77
|
320 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
|
120
|
321 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
322 return computeInstrLatency(DefMI);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
323
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
324 // If we have a per operand scheduling model, check if this def is writing
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
325 // an unbuffered resource. If so, it treated like an in-order cpu.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
326 if (hasInstrSchedModel()) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
327 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
328 if (SCDesc->isValid()) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
329 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
330 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
331 if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->BufferSize)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
332 return 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
333 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
334 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
335 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
336 return 0;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
337 }
|
|
121
|
338
|
|
|
339 static Optional<double>
|
|
|
340 getRThroughputFromItineraries(unsigned schedClass,
|
|
|
341 const InstrItineraryData *IID){
|
|
|
342 Optional<double> Throughput;
|
|
|
343
|
|
|
344 for (const InstrStage *IS = IID->beginStage(schedClass),
|
|
|
345 *E = IID->endStage(schedClass);
|
|
|
346 IS != E; ++IS) {
|
|
|
347 if (IS->getCycles()) {
|
|
|
348 double Temp = countPopulation(IS->getUnits()) * 1.0 / IS->getCycles();
|
|
|
349 Throughput = Throughput.hasValue()
|
|
|
350 ? std::min(Throughput.getValue(), Temp)
|
|
|
351 : Temp;
|
|
|
352 }
|
|
|
353 }
|
|
|
354 if (Throughput.hasValue())
|
|
|
355 // We need reciprocal throughput that's why we return such value.
|
|
|
356 return 1 / Throughput.getValue();
|
|
|
357 return Throughput;
|
|
|
358 }
|
|
|
359
|
|
|
360 static Optional<double>
|
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361 getRThroughputFromInstrSchedModel(const MCSchedClassDesc *SCDesc,
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362 const TargetSubtargetInfo *STI,
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363 const MCSchedModel &SchedModel) {
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364 Optional<double> Throughput;
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365
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366 for (const MCWriteProcResEntry *WPR = STI->getWriteProcResBegin(SCDesc),
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367 *WEnd = STI->getWriteProcResEnd(SCDesc);
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368 WPR != WEnd; ++WPR) {
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369 if (WPR->Cycles) {
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370 unsigned NumUnits =
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371 SchedModel.getProcResource(WPR->ProcResourceIdx)->NumUnits;
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372 double Temp = NumUnits * 1.0 / WPR->Cycles;
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373 Throughput = Throughput.hasValue()
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374 ? std::min(Throughput.getValue(), Temp)
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375 : Temp;
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376 }
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377 }
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378 if (Throughput.hasValue())
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379 // We need reciprocal throughput that's why we return such value.
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380 return 1 / Throughput.getValue();
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381 return Throughput;
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382 }
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383
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384 Optional<double>
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385 TargetSchedModel::computeInstrRThroughput(const MachineInstr *MI) const {
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386 if (hasInstrItineraries())
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387 return getRThroughputFromItineraries(MI->getDesc().getSchedClass(),
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388 getInstrItineraries());
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389 if (hasInstrSchedModel())
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390 return getRThroughputFromInstrSchedModel(resolveSchedClass(MI), STI,
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391 SchedModel);
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392 return Optional<double>();
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393 }
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394
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395 Optional<double>
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396 TargetSchedModel::computeInstrRThroughput(unsigned Opcode) const {
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397 unsigned SchedClass = TII->get(Opcode).getSchedClass();
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398 if (hasInstrItineraries())
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399 return getRThroughputFromItineraries(SchedClass, getInstrItineraries());
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400 if (hasInstrSchedModel()) {
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401 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
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402 if (SCDesc->isValid() && !SCDesc->isVariant())
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403 return getRThroughputFromInstrSchedModel(SCDesc, STI, SchedModel);
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404 }
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405 return Optional<double>();
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406 }
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