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annotate lib/Target/X86/X86Instr3DNow.td @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
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1 //===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file describes the 3DNow! instruction set, which extends MMX to support
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11 // floating point and also adds a few more random instructions for good measure.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
134
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15 let Sched = WriteFAdd in {
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16 def I3DNOW_FALU_ITINS : OpndItins<
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17 IIC_3DNOW_FALU_RR, IIC_3DNOW_FALU_RM
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18 >;
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19 }
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20
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21 let Sched = WriteCvtF2I in {
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22 def I3DNOW_FCVT_F2I_ITINS : OpndItins<
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23 IIC_3DNOW_FCVT_F2I_RR, IIC_3DNOW_FCVT_F2I_RM
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24 >;
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25 }
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26
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27 let Sched = WriteCvtI2F in {
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28 def I3DNOW_FCVT_I2F_ITINS : OpndItins<
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29 IIC_3DNOW_FCVT_I2F_RR, IIC_3DNOW_FCVT_I2F_RM
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30 >;
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31 }
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32
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33 let Sched = WriteVecIMul in {
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34 def I3DNOW_MISC_FUNC_ITINS : OpndItins<
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35 IIC_3DNOW_MISC_FUNC_REG, IIC_3DNOW_MISC_FUNC_MEM
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36 >;
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37 }
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38
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39 let Sched = WriteShuffle in {
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40 def I3DNOW_PSHUF_ITINS : OpndItins<
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41 IIC_MMX_PSHUF, IIC_MMX_PSHUF
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42 >;
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43 }
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44
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45 class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat,
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46 InstrItinClass itin>
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47 : I<o, F, outs, ins, asm, pat, itin>, TB, Requires<[Has3DNow]> {
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48 }
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49
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50 class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat,
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51 InstrItinClass itin>
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52 : I3DNow<o, F, (outs VR64:$dst), ins,
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53 !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat, itin>,
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54 Has3DNow0F0FOpcode {
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55 let Constraints = "$src1 = $dst";
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56 }
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57
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58 class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat,
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59 InstrItinClass itin>
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60 : I3DNow<o, F, (outs VR64:$dst), ins,
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61 !strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat, itin>,
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62 Has3DNow0F0FOpcode;
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63
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64 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, OpndItins itins,
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65 bit Commutable = 0, string Ver = ""> {
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66 let isCommutable = Commutable in
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67 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
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68 [(set VR64:$dst, (!cast<Intrinsic>(
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69 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))],
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70 itins.rr>, Sched<[itins.Sched]>;
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71 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
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72 [(set VR64:$dst, (!cast<Intrinsic>(
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73 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1,
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74 (bitconvert (load_mmx addr:$src2))))], itins.rm>,
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75 Sched<[itins.Sched.Folded, ReadAfterLd]>;
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76 }
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77
134
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78 multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, OpndItins itins,
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79 string Ver = ""> {
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80 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
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81 [(set VR64:$dst, (!cast<Intrinsic>(
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82 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))], itins.rr>,
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83 Sched<[itins.Sched]>;
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84 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn,
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85 [(set VR64:$dst, (!cast<Intrinsic>(
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86 !strconcat("int_x86_3dnow", Ver, "_", Mn))
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87 (bitconvert (load_mmx addr:$src))))], itins.rm>,
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88 Sched<[itins.Sched.Folded, ReadAfterLd]>;
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89 }
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90
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91 defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", I3DNOW_MISC_FUNC_ITINS, 1>;
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92 defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id", I3DNOW_FCVT_F2I_ITINS>;
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93 defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc", I3DNOW_FALU_ITINS>;
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94 defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", I3DNOW_FALU_ITINS, 1>;
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95 defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", I3DNOW_FALU_ITINS, 1>;
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96 defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge", I3DNOW_FALU_ITINS>;
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97 defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt", I3DNOW_FALU_ITINS>;
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98 defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax", I3DNOW_FALU_ITINS>;
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99 defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin", I3DNOW_FALU_ITINS>;
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100 defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", I3DNOW_FALU_ITINS, 1>;
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101 defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp", I3DNOW_FALU_ITINS>;
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102 defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1", I3DNOW_FALU_ITINS>;
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103 defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", I3DNOW_FALU_ITINS>;
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104 defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", I3DNOW_FALU_ITINS>;
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105 defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt", I3DNOW_FALU_ITINS>;
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106 defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", I3DNOW_FALU_ITINS, 1>;
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107 defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", I3DNOW_FALU_ITINS, 1>;
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108 defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", I3DNOW_FCVT_I2F_ITINS>;
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109 defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", I3DNOW_MISC_FUNC_ITINS, 1>;
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110
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111 // FIXME: Is there a better scheduler class for EMMS/FEMMS?
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112 let SchedRW = [WriteMicrocoded] in
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113 def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
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114 [(int_x86_mmx_femms)], IIC_MMX_EMMS>;
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115
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116 // PREFETCHWT1 is supported we want to use it for everything but T0.
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117 def PrefetchWLevel : PatFrag<(ops), (i32 imm), [{
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118 return N->getSExtValue() == 3 || !Subtarget->hasPREFETCHWT1();
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119 }]>;
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120
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121 // Use PREFETCHWT1 for NTA, T2, T1.
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122 def PrefetchWT1Level : ImmLeaf<i32, [{
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123 return Imm < 3;
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124 }]>;
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125
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126 let SchedRW = [WriteLoad] in {
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127 let Predicates = [Has3DNow, NoSSEPrefetch] in
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128 def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
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129 "prefetch\t$addr",
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130 [(prefetch addr:$addr, imm, imm, (i32 1))],
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131 IIC_SSE_PREFETCH>;
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132
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133 def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr",
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134 [(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))],
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135 IIC_SSE_PREFETCH>, TB, Requires<[HasPrefetchW]>;
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136
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137 def PREFETCHWT1 : I<0x0D, MRM2m, (outs), (ins i8mem:$addr), "prefetchwt1\t$addr",
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138 [(prefetch addr:$addr, (i32 1), (i32 PrefetchWT1Level), (i32 1))],
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139 IIC_SSE_PREFETCH>, TB, Requires<[HasPREFETCHWT1]>;
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140 }
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diff changeset
141
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 // "3DNowA" instructions
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
143 defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", I3DNOW_FCVT_F2I_ITINS, "a">;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
144 defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", I3DNOW_FCVT_I2F_ITINS, "a">;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
145 defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", I3DNOW_FALU_ITINS, 0, "a">;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
146 defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", I3DNOW_FALU_ITINS, 0, "a">;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
147 defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", I3DNOW_PSHUF_ITINS, "a">;