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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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3 ; RUN: | FileCheck %s -check-prefix=RV32I
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4
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5 ; Check indexed and unindexed, sext, zext and anyext loads
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6
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7 define i32 @lb(i8 *%a) nounwind {
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8 ; RV32I-LABEL: lb:
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9 ; RV32I: # %bb.0:
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10 ; RV32I-NEXT: lb a1, 0(a0)
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11 ; RV32I-NEXT: lb a0, 1(a0)
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12 ; RV32I-NEXT: ret
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13 %1 = getelementptr i8, i8* %a, i32 1
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14 %2 = load i8, i8* %1
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15 %3 = sext i8 %2 to i32
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16 ; the unused load will produce an anyext for selection
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17 %4 = load volatile i8, i8* %a
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18 ret i32 %3
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19 }
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20
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21 define i32 @lh(i16 *%a) nounwind {
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22 ; RV32I-LABEL: lh:
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23 ; RV32I: # %bb.0:
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24 ; RV32I-NEXT: lh a1, 0(a0)
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25 ; RV32I-NEXT: lh a0, 4(a0)
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26 ; RV32I-NEXT: ret
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27 %1 = getelementptr i16, i16* %a, i32 2
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28 %2 = load i16, i16* %1
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29 %3 = sext i16 %2 to i32
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30 ; the unused load will produce an anyext for selection
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31 %4 = load volatile i16, i16* %a
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32 ret i32 %3
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33 }
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34
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35 define i32 @lw(i32 *%a) nounwind {
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36 ; RV32I-LABEL: lw:
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37 ; RV32I: # %bb.0:
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38 ; RV32I-NEXT: lw a1, 0(a0)
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39 ; RV32I-NEXT: lw a0, 12(a0)
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40 ; RV32I-NEXT: ret
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41 %1 = getelementptr i32, i32* %a, i32 3
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42 %2 = load i32, i32* %1
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43 %3 = load volatile i32, i32* %a
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44 ret i32 %2
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45 }
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46
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47 define i32 @lbu(i8 *%a) nounwind {
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48 ; RV32I-LABEL: lbu:
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49 ; RV32I: # %bb.0:
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50 ; RV32I-NEXT: lbu a1, 0(a0)
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51 ; RV32I-NEXT: lbu a0, 4(a0)
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52 ; RV32I-NEXT: add a0, a0, a1
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53 ; RV32I-NEXT: ret
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54 %1 = getelementptr i8, i8* %a, i32 4
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55 %2 = load i8, i8* %1
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56 %3 = zext i8 %2 to i32
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57 %4 = load volatile i8, i8* %a
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58 %5 = zext i8 %4 to i32
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59 %6 = add i32 %3, %5
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60 ret i32 %6
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61 }
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62
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63 define i32 @lhu(i16 *%a) nounwind {
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64 ; RV32I-LABEL: lhu:
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65 ; RV32I: # %bb.0:
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66 ; RV32I-NEXT: lhu a1, 0(a0)
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67 ; RV32I-NEXT: lhu a0, 10(a0)
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68 ; RV32I-NEXT: add a0, a0, a1
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69 ; RV32I-NEXT: ret
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70 %1 = getelementptr i16, i16* %a, i32 5
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71 %2 = load i16, i16* %1
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72 %3 = zext i16 %2 to i32
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73 %4 = load volatile i16, i16* %a
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74 %5 = zext i16 %4 to i32
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75 %6 = add i32 %3, %5
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76 ret i32 %6
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77 }
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78
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79 ; Check indexed and unindexed stores
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80
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81 define void @sb(i8 *%a, i8 %b) nounwind {
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82 ; RV32I-LABEL: sb:
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83 ; RV32I: # %bb.0:
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84 ; RV32I-NEXT: sb a1, 6(a0)
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85 ; RV32I-NEXT: sb a1, 0(a0)
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86 ; RV32I-NEXT: ret
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87 store i8 %b, i8* %a
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88 %1 = getelementptr i8, i8* %a, i32 6
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89 store i8 %b, i8* %1
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90 ret void
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91 }
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92
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93 define void @sh(i16 *%a, i16 %b) nounwind {
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94 ; RV32I-LABEL: sh:
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95 ; RV32I: # %bb.0:
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96 ; RV32I-NEXT: sh a1, 14(a0)
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97 ; RV32I-NEXT: sh a1, 0(a0)
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98 ; RV32I-NEXT: ret
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99 store i16 %b, i16* %a
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100 %1 = getelementptr i16, i16* %a, i32 7
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101 store i16 %b, i16* %1
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102 ret void
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103 }
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104
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105 define void @sw(i32 *%a, i32 %b) nounwind {
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106 ; RV32I-LABEL: sw:
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107 ; RV32I: # %bb.0:
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108 ; RV32I-NEXT: sw a1, 32(a0)
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109 ; RV32I-NEXT: sw a1, 0(a0)
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110 ; RV32I-NEXT: ret
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111 store i32 %b, i32* %a
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112 %1 = getelementptr i32, i32* %a, i32 8
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113 store i32 %b, i32* %1
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114 ret void
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115 }
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116
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117 ; Check load and store to an i1 location
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118 define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
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119 ; RV32I-LABEL: load_sext_zext_anyext_i1:
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120 ; RV32I: # %bb.0:
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121 ; RV32I-NEXT: lb a1, 0(a0)
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122 ; RV32I-NEXT: lbu a1, 1(a0)
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123 ; RV32I-NEXT: lbu a0, 2(a0)
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124 ; RV32I-NEXT: sub a0, a0, a1
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125 ; RV32I-NEXT: ret
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126 ; sextload i1
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127 %1 = getelementptr i1, i1* %a, i32 1
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128 %2 = load i1, i1* %1
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129 %3 = sext i1 %2 to i32
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130 ; zextload i1
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131 %4 = getelementptr i1, i1* %a, i32 2
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132 %5 = load i1, i1* %4
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133 %6 = zext i1 %5 to i32
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134 %7 = add i32 %3, %6
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135 ; extload i1 (anyext). Produced as the load is unused.
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136 %8 = load volatile i1, i1* %a
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137 ret i32 %7
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138 }
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139
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140 define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
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141 ; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
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142 ; RV32I: # %bb.0:
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143 ; RV32I-NEXT: lb a1, 0(a0)
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144 ; RV32I-NEXT: lbu a1, 1(a0)
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145 ; RV32I-NEXT: lbu a0, 2(a0)
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146 ; RV32I-NEXT: sub a0, a0, a1
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147 ; RV32I-NEXT: ret
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148 ; sextload i1
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149 %1 = getelementptr i1, i1* %a, i32 1
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150 %2 = load i1, i1* %1
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151 %3 = sext i1 %2 to i16
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152 ; zextload i1
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153 %4 = getelementptr i1, i1* %a, i32 2
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154 %5 = load i1, i1* %4
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155 %6 = zext i1 %5 to i16
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156 %7 = add i16 %3, %6
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157 ; extload i1 (anyext). Produced as the load is unused.
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158 %8 = load volatile i1, i1* %a
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159 ret i16 %7
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160 }
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161
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162 ; Check load and store to a global
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163 @G = global i32 0
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164
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165 define i32 @lw_sw_global(i32 %a) nounwind {
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166 ; TODO: the addi should be folded in to the lw/sw operations
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167 ; RV32I-LABEL: lw_sw_global:
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168 ; RV32I: # %bb.0:
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169 ; RV32I-NEXT: lui a1, %hi(G)
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170 ; RV32I-NEXT: addi a2, a1, %lo(G)
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171 ; RV32I-NEXT: lw a1, 0(a2)
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172 ; RV32I-NEXT: sw a0, 0(a2)
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173 ; RV32I-NEXT: lui a2, %hi(G+36)
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174 ; RV32I-NEXT: addi a2, a2, %lo(G+36)
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175 ; RV32I-NEXT: lw a3, 0(a2)
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176 ; RV32I-NEXT: sw a0, 0(a2)
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177 ; RV32I-NEXT: mv a0, a1
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178 ; RV32I-NEXT: ret
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179 %1 = load volatile i32, i32* @G
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180 store i32 %a, i32* @G
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181 %2 = getelementptr i32, i32* @G, i32 9
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182 %3 = load volatile i32, i32* %2
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183 store i32 %a, i32* %2
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184 ret i32 %1
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185 }
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186
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187 ; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
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188 define i32 @lw_sw_constant(i32 %a) nounwind {
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189 ; TODO: the addi should be folded in to the lw/sw
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190 ; RV32I-LABEL: lw_sw_constant:
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191 ; RV32I: # %bb.0:
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192 ; RV32I-NEXT: lui a1, 912092
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193 ; RV32I-NEXT: addi a2, a1, -273
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194 ; RV32I-NEXT: lw a1, 0(a2)
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195 ; RV32I-NEXT: sw a0, 0(a2)
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196 ; RV32I-NEXT: mv a0, a1
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197 ; RV32I-NEXT: ret
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198 %1 = inttoptr i32 3735928559 to i32*
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199 %2 = load volatile i32, i32* %1
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200 store i32 %a, i32* %1
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201 ret i32 %2
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202 }
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