annotate test/CodeGen/X86/vec_sdiv_to_shift.ll @ 134:3a76565eade5 LLVM5.0.1

update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
120
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1172e4bd9c6f update 4.0.0
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2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
1172e4bd9c6f update 4.0.0
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3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
1172e4bd9c6f update 4.0.0
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4 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
0
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5
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6 define <8 x i16> @sdiv_vec8x16(<8 x i16> %var) {
120
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7 ; SSE-LABEL: sdiv_vec8x16:
134
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8 ; SSE: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
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9 ; SSE-NEXT: movdqa %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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10 ; SSE-NEXT: psraw $15, %xmm1
1172e4bd9c6f update 4.0.0
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11 ; SSE-NEXT: psrlw $11, %xmm1
1172e4bd9c6f update 4.0.0
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12 ; SSE-NEXT: paddw %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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13 ; SSE-NEXT: psraw $5, %xmm1
1172e4bd9c6f update 4.0.0
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14 ; SSE-NEXT: movdqa %xmm1, %xmm0
1172e4bd9c6f update 4.0.0
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15 ; SSE-NEXT: retq
1172e4bd9c6f update 4.0.0
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16 ;
1172e4bd9c6f update 4.0.0
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17 ; AVX-LABEL: sdiv_vec8x16:
134
3a76565eade5 update 5.0.1
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18 ; AVX: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
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19 ; AVX-NEXT: vpsraw $15, %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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20 ; AVX-NEXT: vpsrlw $11, %xmm1, %xmm1
1172e4bd9c6f update 4.0.0
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21 ; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
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22 ; AVX-NEXT: vpsraw $5, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
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23 ; AVX-NEXT: retq
0
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24 entry:
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25 %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
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26 ret <8 x i16> %0
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27 }
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28
95
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29 define <8 x i16> @sdiv_vec8x16_minsize(<8 x i16> %var) minsize {
120
1172e4bd9c6f update 4.0.0
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30 ; SSE-LABEL: sdiv_vec8x16_minsize:
134
3a76565eade5 update 5.0.1
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31 ; SSE: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
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32 ; SSE-NEXT: movdqa %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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33 ; SSE-NEXT: psraw $15, %xmm1
1172e4bd9c6f update 4.0.0
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34 ; SSE-NEXT: psrlw $11, %xmm1
1172e4bd9c6f update 4.0.0
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35 ; SSE-NEXT: paddw %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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36 ; SSE-NEXT: psraw $5, %xmm1
1172e4bd9c6f update 4.0.0
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37 ; SSE-NEXT: movdqa %xmm1, %xmm0
1172e4bd9c6f update 4.0.0
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38 ; SSE-NEXT: retq
1172e4bd9c6f update 4.0.0
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39 ;
1172e4bd9c6f update 4.0.0
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40 ; AVX-LABEL: sdiv_vec8x16_minsize:
134
3a76565eade5 update 5.0.1
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41 ; AVX: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
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42 ; AVX-NEXT: vpsraw $15, %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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43 ; AVX-NEXT: vpsrlw $11, %xmm1, %xmm1
1172e4bd9c6f update 4.0.0
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44 ; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
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45 ; AVX-NEXT: vpsraw $5, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
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46 ; AVX-NEXT: retq
95
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47 entry:
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48 %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
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49 ret <8 x i16> %0
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50 }
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51
0
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52 define <4 x i32> @sdiv_vec4x32(<4 x i32> %var) {
120
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53 ; SSE-LABEL: sdiv_vec4x32:
134
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54 ; SSE: # %bb.0: # %entry
120
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55 ; SSE-NEXT: movdqa %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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56 ; SSE-NEXT: psrad $31, %xmm1
1172e4bd9c6f update 4.0.0
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57 ; SSE-NEXT: psrld $28, %xmm1
1172e4bd9c6f update 4.0.0
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58 ; SSE-NEXT: paddd %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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59 ; SSE-NEXT: psrad $4, %xmm1
1172e4bd9c6f update 4.0.0
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60 ; SSE-NEXT: movdqa %xmm1, %xmm0
1172e4bd9c6f update 4.0.0
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61 ; SSE-NEXT: retq
1172e4bd9c6f update 4.0.0
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62 ;
1172e4bd9c6f update 4.0.0
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63 ; AVX-LABEL: sdiv_vec4x32:
134
3a76565eade5 update 5.0.1
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64 ; AVX: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
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65 ; AVX-NEXT: vpsrad $31, %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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66 ; AVX-NEXT: vpsrld $28, %xmm1, %xmm1
1172e4bd9c6f update 4.0.0
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67 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
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68 ; AVX-NEXT: vpsrad $4, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
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69 ; AVX-NEXT: retq
0
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70 entry:
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71 %0 = sdiv <4 x i32> %var, <i32 16, i32 16, i32 16, i32 16>
95c75e76d11b LLVM 3.4
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72 ret <4 x i32> %0
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73 }
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74
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75 define <4 x i32> @sdiv_negative(<4 x i32> %var) {
120
1172e4bd9c6f update 4.0.0
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76 ; SSE-LABEL: sdiv_negative:
134
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77 ; SSE: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
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78 ; SSE-NEXT: movdqa %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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79 ; SSE-NEXT: psrad $31, %xmm1
1172e4bd9c6f update 4.0.0
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80 ; SSE-NEXT: psrld $28, %xmm1
1172e4bd9c6f update 4.0.0
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81 ; SSE-NEXT: paddd %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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82 ; SSE-NEXT: psrad $4, %xmm1
1172e4bd9c6f update 4.0.0
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83 ; SSE-NEXT: pxor %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
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84 ; SSE-NEXT: psubd %xmm1, %xmm0
1172e4bd9c6f update 4.0.0
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85 ; SSE-NEXT: retq
1172e4bd9c6f update 4.0.0
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86 ;
1172e4bd9c6f update 4.0.0
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87 ; AVX-LABEL: sdiv_negative:
134
3a76565eade5 update 5.0.1
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88 ; AVX: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
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89 ; AVX-NEXT: vpsrad $31, %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
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90 ; AVX-NEXT: vpsrld $28, %xmm1, %xmm1
1172e4bd9c6f update 4.0.0
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91 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
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92 ; AVX-NEXT: vpsrad $4, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
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93 ; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
1172e4bd9c6f update 4.0.0
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94 ; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
1172e4bd9c6f update 4.0.0
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95 ; AVX-NEXT: retq
0
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96 entry:
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97 %0 = sdiv <4 x i32> %var, <i32 -16, i32 -16, i32 -16, i32 -16>
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98 ret <4 x i32> %0
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99 }
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100
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101 define <8 x i32> @sdiv8x32(<8 x i32> %var) {
120
1172e4bd9c6f update 4.0.0
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102 ; SSE-LABEL: sdiv8x32:
134
3a76565eade5 update 5.0.1
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103 ; SSE: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
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104 ; SSE-NEXT: movdqa %xmm0, %xmm2
1172e4bd9c6f update 4.0.0
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105 ; SSE-NEXT: psrad $31, %xmm2
1172e4bd9c6f update 4.0.0
mir3636
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106 ; SSE-NEXT: psrld $26, %xmm2
1172e4bd9c6f update 4.0.0
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107 ; SSE-NEXT: paddd %xmm0, %xmm2
1172e4bd9c6f update 4.0.0
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108 ; SSE-NEXT: psrad $6, %xmm2
1172e4bd9c6f update 4.0.0
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109 ; SSE-NEXT: movdqa %xmm1, %xmm3
1172e4bd9c6f update 4.0.0
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110 ; SSE-NEXT: psrad $31, %xmm3
1172e4bd9c6f update 4.0.0
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111 ; SSE-NEXT: psrld $26, %xmm3
1172e4bd9c6f update 4.0.0
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112 ; SSE-NEXT: paddd %xmm1, %xmm3
1172e4bd9c6f update 4.0.0
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113 ; SSE-NEXT: psrad $6, %xmm3
1172e4bd9c6f update 4.0.0
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114 ; SSE-NEXT: movdqa %xmm2, %xmm0
1172e4bd9c6f update 4.0.0
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115 ; SSE-NEXT: movdqa %xmm3, %xmm1
1172e4bd9c6f update 4.0.0
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116 ; SSE-NEXT: retq
1172e4bd9c6f update 4.0.0
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117 ;
1172e4bd9c6f update 4.0.0
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118 ; AVX1-LABEL: sdiv8x32:
134
3a76565eade5 update 5.0.1
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parents: 121
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119 ; AVX1: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
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120 ; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
mir3636
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121 ; AVX1-NEXT: vpsrld $26, %xmm1, %xmm1
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
122 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
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123 ; AVX1-NEXT: vpsrad $6, %xmm1, %xmm1
1172e4bd9c6f update 4.0.0
mir3636
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124 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1172e4bd9c6f update 4.0.0
mir3636
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125 ; AVX1-NEXT: vpsrad $31, %xmm0, %xmm2
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
126 ; AVX1-NEXT: vpsrld $26, %xmm2, %xmm2
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
127 ; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
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128 ; AVX1-NEXT: vpsrad $6, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
129 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
1172e4bd9c6f update 4.0.0
mir3636
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130 ; AVX1-NEXT: retq
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
131 ;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
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132 ; AVX2-LABEL: sdiv8x32:
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
133 ; AVX2: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
134 ; AVX2-NEXT: vpsrad $31, %ymm0, %ymm1
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
135 ; AVX2-NEXT: vpsrld $26, %ymm1, %ymm1
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
136 ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
137 ; AVX2-NEXT: vpsrad $6, %ymm0, %ymm0
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
138 ; AVX2-NEXT: retq
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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139 entry:
95c75e76d11b LLVM 3.4
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140 %0 = sdiv <8 x i32> %var, <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64>
95c75e76d11b LLVM 3.4
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141 ret <8 x i32> %0
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142 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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143
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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144 define <16 x i16> @sdiv16x16(<16 x i16> %var) {
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
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145 ; SSE-LABEL: sdiv16x16:
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
146 ; SSE: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
147 ; SSE-NEXT: movdqa %xmm0, %xmm2
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
148 ; SSE-NEXT: psraw $15, %xmm2
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
149 ; SSE-NEXT: psrlw $14, %xmm2
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
150 ; SSE-NEXT: paddw %xmm0, %xmm2
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
151 ; SSE-NEXT: psraw $2, %xmm2
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
152 ; SSE-NEXT: movdqa %xmm1, %xmm3
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
153 ; SSE-NEXT: psraw $15, %xmm3
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
154 ; SSE-NEXT: psrlw $14, %xmm3
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
155 ; SSE-NEXT: paddw %xmm1, %xmm3
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
156 ; SSE-NEXT: psraw $2, %xmm3
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
157 ; SSE-NEXT: movdqa %xmm2, %xmm0
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
158 ; SSE-NEXT: movdqa %xmm3, %xmm1
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
159 ; SSE-NEXT: retq
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
160 ;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
161 ; AVX1-LABEL: sdiv16x16:
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
162 ; AVX1: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
163 ; AVX1-NEXT: vpsraw $15, %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
164 ; AVX1-NEXT: vpsrlw $14, %xmm1, %xmm1
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
165 ; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm1
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
166 ; AVX1-NEXT: vpsraw $2, %xmm1, %xmm1
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
167 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
168 ; AVX1-NEXT: vpsraw $15, %xmm0, %xmm2
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
169 ; AVX1-NEXT: vpsrlw $14, %xmm2, %xmm2
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
170 ; AVX1-NEXT: vpaddw %xmm2, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
171 ; AVX1-NEXT: vpsraw $2, %xmm0, %xmm0
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
172 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
173 ; AVX1-NEXT: retq
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
174 ;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
175 ; AVX2-LABEL: sdiv16x16:
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
176 ; AVX2: # %bb.0: # %entry
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
177 ; AVX2-NEXT: vpsraw $15, %ymm0, %ymm1
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
178 ; AVX2-NEXT: vpsrlw $14, %ymm1, %ymm1
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
179 ; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
180 ; AVX2-NEXT: vpsraw $2, %ymm0, %ymm0
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
181 ; AVX2-NEXT: retq
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 entry:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 %a0 = sdiv <16 x i16> %var, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 ret <16 x i16> %a0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
186
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
187 ; Div-by-0 in any lane is UB.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
188
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
189 define <4 x i32> @sdiv_non_splat(<4 x i32> %x) {
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
190 ; SSE-LABEL: sdiv_non_splat:
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
191 ; SSE: # %bb.0:
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
192 ; SSE-NEXT: retq
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
193 ;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
194 ; AVX-LABEL: sdiv_non_splat:
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
195 ; AVX: # %bb.0:
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
196 ; AVX-NEXT: retq
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
197 %y = sdiv <4 x i32> %x, <i32 2, i32 0, i32 0, i32 0>
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
198 ret <4 x i32> %y
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
199 }