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annotate test/CodeGen/AMDGPU/trunc.ll @ 146:3fc4d5c3e21e

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set tail call flag for code segment in CGCAll
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 23 Dec 2018 19:23:36 +0900
parents 803732b1fca8
children c2174574ed3a
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
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4
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5 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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6
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7 define amdgpu_kernel void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
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8 ; GCN-LABEL: {{^}}trunc_i64_to_i32_store:
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9 ; GCN: s_load_dword [[SLOAD:s[0-9]+]], s[0:1],
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10 ; GCN: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
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11 ; SI: buffer_store_dword [[VLOAD]]
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12 ; VI: flat_store_dword v[{{[0-9:]+}}], [[VLOAD]]
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13
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14 ; EG-LABEL: {{^}}trunc_i64_to_i32_store:
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15 ; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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16 ; EG: LSHR
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17 ; EG-NEXT: 2(
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18
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19 %result = trunc i64 %in to i32 store i32 %result, i32 addrspace(1)* %out, align 4
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20 ret void
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21 }
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23 ; GCN-LABEL: {{^}}trunc_load_shl_i64:
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24 ; GCN-DAG: s_load_dwordx2
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25 ; GCN-DAG: s_load_dword [[SREG:s[0-9]+]],
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26 ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
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27 ; GCN: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
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28 ; SI: buffer_store_dword [[VSHL]]
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29 ; VI: flat_store_dword v[{{[0-9:]+}}], [[VSHL]]
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30
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31 define amdgpu_kernel void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) {
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32 %b = shl i64 %a, 2
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33 %result = trunc i64 %b to i32
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34 store i32 %result, i32 addrspace(1)* %out, align 4
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35 ret void
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36 }
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37
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38 ; GCN-LABEL: {{^}}trunc_shl_i64:
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39 ; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
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40 ; VI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
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41 ; GCN: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
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42 ; GCN: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
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43 ; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
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44 ; GCN: s_addc_u32
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45 ; SI: buffer_store_dword v[[LO_VREG]],
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46 ; VI: flat_store_dword v[{{[0-9:]+}}], v[[LO_VREG]]
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47 ; GCN: v_mov_b32_e32
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48 ; GCN: v_mov_b32_e32
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49 define amdgpu_kernel void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {
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50 %aa = add i64 %a, 234 ; Prevent shrinking store.
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51 %b = shl i64 %aa, 2
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52 %result = trunc i64 %b to i32
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53 store i32 %result, i32 addrspace(1)* %out, align 4
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54 store i64 %b, i64 addrspace(1)* %out2, align 8 ; Prevent reducing ops to 32-bits
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55 ret void
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56 }
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57
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58 ; GCN-LABEL: {{^}}trunc_i32_to_i1:
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59 ; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
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60 define amdgpu_kernel void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {
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61 %a = load i32, i32 addrspace(1)* %ptr, align 4
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62 %trunc = trunc i32 %a to i1
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63 %result = select i1 %trunc, i32 1, i32 0
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64 store i32 %result, i32 addrspace(1)* %out, align 4
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65 ret void
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66 }
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67
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68 ; GCN-LABEL: {{^}}trunc_i8_to_i1:
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69 ; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
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70 define amdgpu_kernel void @trunc_i8_to_i1(i8 addrspace(1)* %out, i8 addrspace(1)* %ptr) {
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71 %a = load i8, i8 addrspace(1)* %ptr, align 4
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72 %trunc = trunc i8 %a to i1
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73 %result = select i1 %trunc, i8 1, i8 0
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74 store i8 %result, i8 addrspace(1)* %out, align 4
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75 ret void
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76 }
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77
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78 ; GCN-LABEL: {{^}}sgpr_trunc_i16_to_i1:
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79 ; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
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80 define amdgpu_kernel void @sgpr_trunc_i16_to_i1(i16 addrspace(1)* %out, i16 %a) {
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81 %trunc = trunc i16 %a to i1
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82 %result = select i1 %trunc, i16 1, i16 0
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83 store i16 %result, i16 addrspace(1)* %out, align 4
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84 ret void
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85 }
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86
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87 ; GCN-LABEL: {{^}}sgpr_trunc_i32_to_i1:
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88 ; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
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89 define amdgpu_kernel void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
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90 %trunc = trunc i32 %a to i1
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91 %result = select i1 %trunc, i32 1, i32 0
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92 store i32 %result, i32 addrspace(1)* %out, align 4
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93 ret void
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94 }
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121
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96 ; GCN-LABEL: {{^}}s_trunc_i64_to_i1:
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97 ; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb
121
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98 ; VI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x2c
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99 ; GCN: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]
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100 ; GCN: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}
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101 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]
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102 define amdgpu_kernel void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 %x) {
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103 %trunc = trunc i64 %x to i1
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104 %sel = select i1 %trunc, i32 63, i32 -12
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105 store i32 %sel, i32 addrspace(1)* %out
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106 ret void
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107 }
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108
121
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109 ; GCN-LABEL: {{^}}v_trunc_i64_to_i1:
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110 ; SI: buffer_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
121
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111 ; VI: flat_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
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112 ; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
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113 ; GCN: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]
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114 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
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115 define amdgpu_kernel void @v_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {
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116 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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117 %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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118 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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119 %x = load i64, i64 addrspace(1)* %gep
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120
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121 %trunc = trunc i64 %x to i1
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122 %sel = select i1 %trunc, i32 63, i32 -12
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123 store i32 %sel, i32 addrspace(1)* %out.gep
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124 ret void
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125 }