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annotate lib/Target/Mips/MSA.txt @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children
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1 Code Generation Notes for MSA
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2 =============================
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3
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4 Intrinsics are lowered to SelectionDAG nodes where possible in order to enable
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5 optimisation, reduce the size of the ISel matcher, and reduce repetition in
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6 the implementation. In a small number of cases, this can cause different
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7 (semantically equivalent) instructions to be used in place of the requested
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8 instruction, even when no optimisation has taken place.
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9
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10 Instructions
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11 ============
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12
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13 This section describes any quirks of instruction selection for MSA. For
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14 example, two instructions might be equally valid for some given IR and one is
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15 chosen in preference to the other.
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16
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17 bclri.b:
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18 It is not possible to emit bclri.b since andi.b covers exactly the
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19 same cases. andi.b should use fractionally less power than bclri.b in
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20 most hardware implementations so it is used in preference to bclri.b.
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21
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22 vshf.w:
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23 It is not possible to emit vshf.w when the shuffle description is
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24 constant since shf.w covers exactly the same cases. shf.w is used
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25 instead. It is also impossible for the shuffle description to be
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26 unknown at compile-time due to the definition of shufflevector in
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27 LLVM IR.
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28
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29 vshf.[bhwd]
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30 When the shuffle description describes a splat operation, splat.[bhwd]
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31 instructions will be selected instead of vshf.[bhwd]. Unlike the ilv*,
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32 and pck* instructions, this is matched from MipsISD::VSHF instead of
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33 a special-case MipsISD node.
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34
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35 ilvl.d, pckev.d:
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36 It is not possible to emit ilvl.d, or pckev.d since ilvev.d covers the
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37 same shuffle. ilvev.d will be emitted instead.
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38
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39 ilvr.d, ilvod.d, pckod.d:
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40 It is not possible to emit ilvr.d, or pckod.d since ilvod.d covers the
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41 same shuffle. ilvod.d will be emitted instead.
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42
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43 splat.[bhwd]
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44 The intrinsic will work as expected. However, unlike other intrinsics
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45 it lowers directly to MipsISD::VSHF instead of using common IR.
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46
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47 splati.w:
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48 It is not possible to emit splati.w since shf.w covers the same cases.
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49 shf.w will be emitted instead.
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50
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51 copy_s.w:
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52 On MIPS32, the copy_u.d intrinsic will emit this instruction instead of
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53 copy_u.w. This is semantically equivalent since the general-purpose
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54 register file is 32-bits wide.
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55
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56 binsri.[bhwd], binsli.[bhwd]:
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57 These two operations are equivalent to each other with the operands
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58 swapped and condition inverted. The compiler may use either one as
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59 appropriate.
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60 Furthermore, the compiler may use bsel.[bhwd] for some masks that do
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61 not survive the legalization process (this is a bug and will be fixed).
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62
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63 bmnz.v, bmz.v, bsel.v:
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64 These three operations differ only in the operand that is tied to the
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65 result and the order of the operands.
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66 It is (currently) not possible to emit bmz.v, or bsel.v since bmnz.v is
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67 the same operation and will be emitted instead.
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68 In future, the compiler may choose between these three instructions
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69 according to register allocation.
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70 These three operations can be very confusing so here is a mapping
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71 between the instructions and the vselect node in one place:
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72 bmz.v wd, ws, wt/i8 -> (vselect wt/i8, wd, ws)
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73 bmnz.v wd, ws, wt/i8 -> (vselect wt/i8, ws, wd)
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74 bsel.v wd, ws, wt/i8 -> (vselect wd, wt/i8, ws)
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75
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76 bmnzi.b, bmzi.b:
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77 Like their non-immediate counterparts, bmnzi.v and bmzi.v are the same
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78 operation with the operands swapped. bmnzi.v will (currently) be emitted
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79 for both cases.
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80
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81 bseli.v:
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82 Unlike the non-immediate versions, bseli.v is distinguishable from
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83 bmnzi.b and bmzi.b and can be emitted.