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annotate lib/Target/Mips/Mips.td @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents e4204d083e25
children 60c9769439b8
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1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 // This is the top level entry point for the Mips target.
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10 //===----------------------------------------------------------------------===//
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11
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12 //===----------------------------------------------------------------------===//
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13 // Target-independent interfaces
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14 //===----------------------------------------------------------------------===//
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15
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16 include "llvm/Target/Target.td"
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17
77
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18 // The overall idea of the PredicateControl class is to chop the Predicates list
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19 // into subsets that are usually overridden independently. This allows
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20 // subclasses to partially override the predicates of their superclasses without
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21 // having to re-add all the existing predicates.
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22 class PredicateControl {
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23 // Predicates for the encoding scheme in use such as HasStdEnc
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24 list<Predicate> EncodingPredicates = [];
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25 // Predicates for the GPR size such as IsGP64bit
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26 list<Predicate> GPRPredicates = [];
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27 // Predicates for the FGR size and layout such as IsFP64bit
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28 list<Predicate> FGRPredicates = [];
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29 // Predicates for the instruction group membership such as ISA's and ASE's
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30 list<Predicate> InsnPredicates = [];
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31 // Predicates for anything else
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32 list<Predicate> AdditionalPredicates = [];
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33 list<Predicate> Predicates = !listconcat(EncodingPredicates,
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34 GPRPredicates,
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35 FGRPredicates,
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36 InsnPredicates,
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37 AdditionalPredicates);
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38 }
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39
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40 // Like Requires<> but for the AdditionalPredicates list
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41 class AdditionalRequires<list<Predicate> preds> {
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42 list<Predicate> AdditionalPredicates = preds;
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43 }
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44
0
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45 //===----------------------------------------------------------------------===//
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46 // Register File, Calling Conv, Instruction Descriptions
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47 //===----------------------------------------------------------------------===//
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48
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49 include "MipsRegisterInfo.td"
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50 include "MipsSchedule.td"
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51 include "MipsInstrInfo.td"
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52 include "MipsCallingConv.td"
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53
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54 def MipsInstrInfo : InstrInfo;
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55
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56 //===----------------------------------------------------------------------===//
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57 // Mips Subtarget features //
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58 //===----------------------------------------------------------------------===//
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59
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60 def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
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61 "Disable SVR4-style position-independent code.">;
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62 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
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63 "General Purpose Registers are 64-bit wide.">;
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64 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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65 "Support 64-bit FP registers.">;
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66 def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
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67 "Support for FPXX.">;
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68 def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
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69 "IEEE 754-2008 NaN encoding.">;
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70 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
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71 "true", "Only supports single precision float">;
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72 def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
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73 "Enable o32 ABI">;
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74 def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32",
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75 "Enable n32 ABI">;
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76 def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64",
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77 "Enable n64 ABI">;
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78 def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
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79 "Enable eabi ABI">;
77
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80 def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
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81 "Disable odd numbered single-precision "
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82 "registers">;
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83 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
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84 "true", "Enable vector FPU instructions.">;
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85 def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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86 "Mips I ISA Support [highly experimental]">;
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87 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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88 "Mips II ISA Support [highly experimental]",
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89 [FeatureMips1]>;
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90 def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
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91 "Subset of MIPS-III that is also in MIPS32 "
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92 "[highly experimental]">;
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93 def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
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94 "Subset of MIPS-III that is also in MIPS32r2 "
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95 "[highly experimental]">;
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96 def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
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97 "MIPS III ISA Support [highly experimental]",
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98 [FeatureMips2, FeatureMips3_32,
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99 FeatureMips3_32r2, FeatureGP64Bit,
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100 FeatureFP64Bit]>;
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101 def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
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102 "Subset of MIPS-IV that is also in MIPS32 "
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103 "[highly experimental]">;
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104 def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
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105 "Subset of MIPS-IV that is also in MIPS32r2 "
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106 "[highly experimental]">;
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107 def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
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108 "Mips4", "MIPS IV ISA Support",
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109 [FeatureMips3, FeatureMips4_32,
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110 FeatureMips4_32r2]>;
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111 def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
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112 "Subset of MIPS-V that is also in MIPS32r2 "
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113 "[highly experimental]">;
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114 def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
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115 "MIPS V ISA Support [highly experimental]",
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116 [FeatureMips4, FeatureMips5_32r2]>;
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117 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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118 "Mips32 ISA Support",
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119 [FeatureMips2, FeatureMips3_32,
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120 FeatureMips4_32]>;
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121 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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122 "Mips32r2", "Mips32r2 ISA Support",
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123 [FeatureMips3_32r2, FeatureMips4_32r2,
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124 FeatureMips5_32r2, FeatureMips32]>;
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125 def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
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126 "Mips32r6",
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127 "Mips32r6 ISA Support [experimental]",
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128 [FeatureMips32r2, FeatureFP64Bit,
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129 FeatureNaN2008]>;
0
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130 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
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131 "Mips64", "Mips64 ISA Support",
77
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132 [FeatureMips5, FeatureMips32]>;
0
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133 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
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134 "Mips64r2", "Mips64r2 ISA Support",
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135 [FeatureMips64, FeatureMips32r2]>;
77
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136 def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
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137 "Mips64r6",
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138 "Mips64r6 ISA Support [experimental]",
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139 [FeatureMips32r6, FeatureMips64r2,
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140 FeatureNaN2008]>;
0
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141
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142 def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
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143 "Mips16 mode">;
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144
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145 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
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146 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
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147 "Mips DSP-R2 ASE", [FeatureDSP]>;
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148
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149 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
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150
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151 def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
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152 "microMips mode">;
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153
77
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154 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
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155 "true", "Octeon cnMIPS Support",
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156 [FeatureMips64r2]>;
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157
0
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158 //===----------------------------------------------------------------------===//
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159 // Mips processors supported.
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160 //===----------------------------------------------------------------------===//
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161
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162 class Proc<string Name, list<SubtargetFeature> Features>
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163 : Processor<Name, MipsGenericItineraries, Features>;
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164
77
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165 def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
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166 def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
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167 def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
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168 def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
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169 def : Proc<"mips32r6", [FeatureMips32r6, FeatureO32]>;
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170
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171 def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
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172 def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
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173 def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
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174 def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
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175 def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
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176 def : Proc<"mips64r6", [FeatureMips64r6, FeatureN64]>;
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177 def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
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178 def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
0
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179
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180 def MipsAsmParser : AsmParser {
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181 let ShouldEmitMatchRegisterName = 0;
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182 let MnemonicContainsDot = 1;
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183 }
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184
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185 def MipsAsmParserVariant : AsmParserVariant {
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186 int Variant = 0;
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187
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188 // Recognize hard coded registers.
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189 string RegisterPrefix = "$";
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190 }
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191
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192 def Mips : Target {
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193 let InstructionSet = MipsInstrInfo;
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194 let AssemblyParsers = [MipsAsmParser];
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195 let AssemblyParserVariants = [MipsAsmParserVariant];
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196 }