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77
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1 ; Check that [sl]dc1 are normally emitted. MIPS32r2 should have [sl]dxc1 too.
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2 ; RUN: llc -march=mipsel -mcpu=mips32 < %s | \
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3 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1-LDC1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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4 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | \
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77
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5 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2-LDXC1
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6 ; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | \
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7 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6-LDC1
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8
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9 ; Check that -mno-ldc1-sdc1 disables [sl]dc1
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10 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
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11 ; RUN: -mcpu=mips32 < %s | \
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12 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \
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13 ; RUN: -check-prefix=32R1-LE -check-prefix=32R1-LE-PIC
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14 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
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15 ; RUN: -mcpu=mips32r2 < %s | \
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16 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \
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17 ; RUN: -check-prefix=32R2-LE -check-prefix=32R2-LE-PIC
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18 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
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19 ; RUN: -mcpu=mips32r6 < %s | \
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20 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \
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21 ; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-PIC
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22
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23 ; Check again for big-endian
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24 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
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25 ; RUN: -mcpu=mips32 < %s | \
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26 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \
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27 ; RUN: -check-prefix=32R1-BE -check-prefix=32R1-BE-PIC
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28 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
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29 ; RUN: -mcpu=mips32r2 < %s | \
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30 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \
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31 ; RUN: -check-prefix=32R2-BE -check-prefix=32R2-BE-PIC
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32 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
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33 ; RUN: -mcpu=mips32r6 < %s | \
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34 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \
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35 ; RUN: -check-prefix=32R6-BE -check-prefix=32R6-BE-PIC
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36
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37 ; Check again for the static relocation model
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38 ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
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39 ; RUN: -mcpu=mips32 < %s | \
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40 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \
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41 ; RUN: -check-prefix=32R1-LE -check-prefix=32R1-LE-STATIC
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42 ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
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43 ; RUN: -mcpu=mips32r2 < %s | \
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44 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \
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45 ; RUN: -check-prefix=32R2-LE -check-prefix=32R2-LE-STATIC
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46 ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
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47 ; RUN: -mcpu=mips32r6 < %s | \
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48 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \
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49 ; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-STATIC
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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50
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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51 @g0 = common global double 0.000000e+00, align 8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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52
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77
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53 ; ALL-LABEL: test_ldc1:
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54
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55 ; 32R1-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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56 ; 32R1-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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57 ; 32R1-LE-PIC-DAG: mtc1 $[[R0]], $f0
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58 ; 32R1-LE-PIC-DAG: mtc1 $[[R1]], $f1
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59
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60 ; 32R2-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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61 ; 32R2-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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62 ; 32R2-LE-PIC-DAG: mtc1 $[[R0]], $f0
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63 ; 32R2-LE-PIC-DAG: mthc1 $[[R1]], $f0
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64
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65 ; 32R6-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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66 ; 32R6-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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67 ; 32R6-LE-PIC-DAG: mtc1 $[[R0]], $f0
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68 ; 32R6-LE-PIC-DAG: mthc1 $[[R1]], $f0
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69
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70 ; 32R1-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
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71 ; 32R1-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
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72 ; 32R1-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
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73 ; 32R1-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]])
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74 ; 32R1-LE-STATIC-DAG: mtc1 $[[R1]], $f0
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75 ; 32R1-LE-STATIC-DAG: mtc1 $[[R3]], $f1
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76
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77 ; 32R2-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
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78 ; 32R2-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
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79 ; 32R2-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
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80 ; 32R2-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]])
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81 ; 32R2-LE-STATIC-DAG: mtc1 $[[R1]], $f0
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82 ; 32R2-LE-STATIC-DAG: mthc1 $[[R3]], $f0
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83
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84 ; 32R6-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
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85 ; 32R6-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
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86 ; 32R6-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
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87 ; 32R6-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]])
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88 ; 32R6-LE-STATIC-DAG: mtc1 $[[R1]], $f0
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89 ; 32R6-LE-STATIC-DAG: mthc1 $[[R3]], $f0
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90
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91 ; 32R1-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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92 ; 32R1-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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93 ; 32R1-BE-PIC-DAG: mtc1 $[[R1]], $f0
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94 ; 32R1-BE-PIC-DAG: mtc1 $[[R0]], $f1
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95
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96 ; 32R2-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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97 ; 32R2-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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98 ; 32R2-BE-PIC-DAG: mtc1 $[[R1]], $f0
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99 ; 32R2-BE-PIC-DAG: mthc1 $[[R0]], $f0
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100
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101 ; 32R6-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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102 ; 32R6-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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103 ; 32R6-BE-PIC-DAG: mtc1 $[[R1]], $f0
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104 ; 32R6-BE-PIC-DAG: mthc1 $[[R0]], $f0
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105
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106 ; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}})
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107
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108 ; 32R2-LDXC1: ldc1 $f0, 0(${{[0-9]+}})
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109
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110 ; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}})
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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111
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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112 define double @test_ldc1() {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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113 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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114 %0 = load double* @g0, align 8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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115 ret double %0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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116 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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117
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77
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118 ; ALL-LABEL: test_sdc1:
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119
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120 ; 32R1-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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121 ; 32R1-LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
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122 ; 32R1-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
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123 ; 32R1-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
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124
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125 ; 32R2-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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126 ; 32R2-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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127 ; 32R2-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
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128 ; 32R2-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
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129
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130 ; 32R6-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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131 ; 32R6-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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132 ; 32R6-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
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133 ; 32R6-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
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134
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135 ; 32R1-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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136 ; 32R1-LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
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137 ; 32R1-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
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138 ; 32R1-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
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139 ; 32R1-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
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140 ; 32R1-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
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141
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142 ; 32R2-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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143 ; 32R2-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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144 ; 32R2-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
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145 ; 32R2-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
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146 ; 32R2-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
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147 ; 32R2-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
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148
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149 ; 32R6-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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150 ; 32R6-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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151 ; 32R6-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
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152 ; 32R6-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
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153 ; 32R6-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
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154 ; 32R6-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
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155
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156 ; 32R1-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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157 ; 32R1-BE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
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158 ; 32R1-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
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159 ; 32R1-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
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160
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161 ; 32R2-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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162 ; 32R2-BE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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163 ; 32R2-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
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164 ; 32R2-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
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165
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166 ; 32R6-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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167 ; 32R6-BE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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168 ; 32R6-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
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169 ; 32R6-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
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170
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171 ; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
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172
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173 ; 32R2-LDXC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
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174
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175 ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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176
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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177 define void @test_sdc1(double %a) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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178 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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179 store double %a, double* @g0, align 8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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180 ret void
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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181 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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182
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183 ; ALL-LABEL: test_ldxc1:
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184
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77
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185 ; 32R1-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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186 ; 32R1-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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187 ; 32R1-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}})
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188 ; 32R1-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}})
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189 ; 32R1-DAG: mtc1 $[[R0]], $f0
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190 ; 32R1-DAG: mtc1 $[[R1]], $f1
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191
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192 ; 32R2-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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193 ; 32R2-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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194 ; 32R2-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}})
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195 ; 32R2-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}})
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196 ; 32R2-DAG: mtc1 $[[R0]], $f0
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197 ; 32R2-DAG: mthc1 $[[R1]], $f0
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198
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199 ; 32R6-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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200 ; 32R6-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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201 ; 32R6-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}})
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202 ; 32R6-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}})
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203 ; 32R6-DAG: mtc1 $[[R0]], $f0
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204 ; 32R6-DAG: mthc1 $[[R1]], $f0
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205
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206 ; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}})
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207
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208 ; 32R2-LDXC1: sll $[[OFFSET:[0-9]+]], $5, 3
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209 ; 32R2-LDXC1: ldxc1 $f0, $[[OFFSET]]($4)
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210
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211 ; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}})
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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212
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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213 define double @test_ldxc1(double* nocapture readonly %a, i32 %i) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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214 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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215 %arrayidx = getelementptr inbounds double* %a, i32 %i
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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216 %0 = load double* %arrayidx, align 8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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217 ret double %0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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218 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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219
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220 ; ALL-LABEL: test_sdxc1:
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221
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222 ; 32R1-DAG: mfc1 $[[R0:[0-9]+]], $f12
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223 ; 32R1-DAG: mfc1 $[[R1:[0-9]+]], $f13
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224 ; 32R1-DAG: sw $[[R0]], 0(${{[0-9]+}})
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225 ; 32R1-DAG: sw $[[R1]], 4(${{[0-9]+}})
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226
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227 ; 32R2-DAG: mfc1 $[[R0:[0-9]+]], $f12
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228 ; 32R2-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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229 ; 32R2-DAG: sw $[[R0]], 0(${{[0-9]+}})
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230 ; 32R2-DAG: sw $[[R1]], 4(${{[0-9]+}})
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231
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232 ; 32R6-DAG: mfc1 $[[R0:[0-9]+]], $f12
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233 ; 32R6-DAG: mfhc1 $[[R1:[0-9]+]], $f12
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234 ; 32R6-DAG: sw $[[R0]], 0(${{[0-9]+}})
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235 ; 32R6-DAG: sw $[[R1]], 4(${{[0-9]+}})
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236
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237 ; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
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238
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239 ; 32R2-LDXC1: sll $[[OFFSET:[0-9]+]], $7, 3
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240 ; 32R2-LDXC1: sdxc1 $f{{[0-9]+}}, $[[OFFSET]]($6)
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241
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242 ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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243
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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244 define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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245 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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246 %arrayidx = getelementptr inbounds double* %a, i32 %i
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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247 store double %b, double* %arrayidx, align 8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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248 ret void
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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249 }
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