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150
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1 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1010 -check-prefix=GCN %s
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2
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3 # GCN-LABEL: {{^}}name: vop1_instructions
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4
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5 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec
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221
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6 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec
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7 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $mode, implicit $exec
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8 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $mode, implicit $exec
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9 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec
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150
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10
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11 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 6, 0, 5, implicit $exec
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221
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12 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec
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13 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $mode, implicit $exec
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14 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $mode, implicit $exec
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15 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec
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150
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16
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221
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17 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $mode, implicit $exec
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18 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 1, 0, 5, 0, 5, implicit $mode, implicit $exec
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19 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 1, %{{[0-9]+}}, 0, 5, 0, 5, implicit $mode, implicit $exec
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20 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 1, 5, 0, 5, implicit $mode, implicit $exec
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150
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21
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22 ---
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23 name: vop1_instructions
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24 tracksRegLiveness: true
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25 registers:
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26 - { id: 0, class: vreg_64 }
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27 - { id: 1, class: vreg_64 }
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28 - { id: 2, class: sreg_64 }
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29 - { id: 3, class: vgpr_32 }
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30 - { id: 4, class: sreg_32_xm0 }
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31 - { id: 5, class: sreg_32_xm0 }
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32 - { id: 6, class: sreg_32_xm0 }
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33 - { id: 7, class: sreg_32_xm0 }
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34 - { id: 8, class: sreg_32 }
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35 - { id: 9, class: vgpr_32 }
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36 - { id: 10, class: vgpr_32 }
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37 - { id: 11, class: vgpr_32 }
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38 - { id: 12, class: vgpr_32 }
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39 - { id: 13, class: vgpr_32 }
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40 - { id: 14, class: vgpr_32 }
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41 - { id: 15, class: vgpr_32 }
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42 - { id: 16, class: vgpr_32 }
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43 - { id: 17, class: vgpr_32 }
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44 - { id: 18, class: vgpr_32 }
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45 - { id: 19, class: vgpr_32 }
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46 - { id: 20, class: vgpr_32 }
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47 - { id: 21, class: vgpr_32 }
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48 - { id: 22, class: vgpr_32 }
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49 - { id: 23, class: vgpr_32 }
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50 - { id: 24, class: vgpr_32 }
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51 - { id: 25, class: vgpr_32 }
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52 - { id: 26, class: vgpr_32 }
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53 - { id: 27, class: vgpr_32 }
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54 - { id: 28, class: vgpr_32 }
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55 - { id: 29, class: vgpr_32 }
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56 - { id: 30, class: vgpr_32 }
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57 - { id: 31, class: vgpr_32 }
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58 - { id: 32, class: vgpr_32 }
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59 - { id: 33, class: vgpr_32 }
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60 - { id: 34, class: vgpr_32 }
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61 - { id: 35, class: vgpr_32 }
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62 - { id: 36, class: vgpr_32 }
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63 - { id: 37, class: vgpr_32 }
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64 - { id: 38, class: vgpr_32 }
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65 - { id: 39, class: vgpr_32 }
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66 - { id: 40, class: vgpr_32 }
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67 - { id: 41, class: vgpr_32 }
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68 - { id: 42, class: vgpr_32 }
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69 - { id: 43, class: vgpr_32 }
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70 - { id: 44, class: vgpr_32 }
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71 - { id: 45, class: vgpr_32 }
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72 - { id: 46, class: vgpr_32 }
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73 - { id: 47, class: vgpr_32 }
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74 - { id: 48, class: vgpr_32 }
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75 - { id: 100, class: vgpr_32 }
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76 body: |
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77 bb.0:
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78 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
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79
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80 %2 = COPY $sgpr30_sgpr31
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81 %1 = COPY $vgpr2_vgpr3
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82 %0 = COPY $vgpr0_vgpr1
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223
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83 %3 = FLAT_LOAD_DWORD %1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))
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150
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84
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85 %5 = S_MOV_B32 65535
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86 %6 = S_MOV_B32 65535
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87
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88 %10 = V_LSHRREV_B32_e64 16, %3, implicit $exec
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89 %11 = V_MOV_B32_e32 %10, implicit $exec
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90 %12 = V_LSHLREV_B32_e64 16, %11, implicit $exec
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221
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91 %14 = V_FRACT_F32_e32 123, implicit $mode, implicit $exec
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150
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92 %15 = V_LSHLREV_B32_e64 16, %14, implicit $exec
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93 %16 = V_LSHRREV_B32_e64 16, %15, implicit $exec
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221
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94 %17 = V_SIN_F32_e32 %16, implicit $mode, implicit $exec
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150
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95 %18 = V_LSHLREV_B32_e64 16, %17, implicit $exec
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96 %19 = V_LSHRREV_B32_e64 16, %18, implicit $exec
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221
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97 %20 = V_CVT_U32_F32_e32 %19, implicit $mode, implicit $exec
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150
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98 %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec
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221
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99 %23 = V_CVT_F32_I32_e32 123, implicit $mode, implicit $exec
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150
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100 %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec
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101
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102 %25 = V_LSHRREV_B32_e64 16, %3, implicit $exec
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103 %26 = V_MOV_B32_e64 %25, implicit $exec
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104 %26 = V_LSHLREV_B32_e64 16, %26, implicit $exec
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221
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105 %27 = V_FRACT_F32_e64 0, %6, 0, 0, implicit $mode, implicit $exec
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150
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106 %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec
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107 %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec
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221
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108 %30 = V_SIN_F32_e64 0, %29, 0, 0, implicit $mode, implicit $exec
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150
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109 %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec
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110 %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec
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221
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111 %33 = V_CVT_U32_F32_e64 0, %32, 0, 0, implicit $mode, implicit $exec
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150
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112 %34 = V_LSHLREV_B32_e64 16, %33, implicit $exec
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221
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113 %35 = V_CVT_F32_I32_e64 %6, 0, 0, implicit $mode, implicit $exec
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150
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114 %36 = V_LSHLREV_B32_e64 16, %35, implicit $exec
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115
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116
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117 %37 = V_LSHRREV_B32_e64 16, %36, implicit $exec
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221
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118 %38 = V_FRACT_F32_e64 1, %37, 0, 0, implicit $mode, implicit $exec
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150
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119 %39 = V_LSHLREV_B32_e64 16, %38, implicit $exec
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120 %40 = V_LSHRREV_B32_e64 16, %39, implicit $exec
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221
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121 %41 = V_SIN_F32_e64 0, %40, 1, 0, implicit $mode, implicit $exec
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150
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122 %42 = V_LSHLREV_B32_e64 16, %41, implicit $exec
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123 %43 = V_LSHRREV_B32_e64 16, %42, implicit $exec
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221
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124 %44 = V_CVT_U32_F32_e64 1, %43, 0, 0, implicit $mode, implicit $exec
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150
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125 %45 = V_LSHLREV_B32_e64 16, %44, implicit $exec
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126 %46 = V_LSHRREV_B32_e64 16, %45, implicit $exec
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221
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127 %47 = V_CVT_F32_I32_e64 %46, 0, 1, implicit $mode, implicit $exec
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150
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128 %48 = V_LSHLREV_B32_e64 16, %47, implicit $exec
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129
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130
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131 %100 = V_MOV_B32_e32 %48, implicit $exec
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132
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223
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133 FLAT_STORE_DWORD %0, %100, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))
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150
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134 $sgpr30_sgpr31 = COPY %2
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135 S_SETPC_B64_return $sgpr30_sgpr31
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136
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137 ...
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138 ---
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139 # GCN-LABEL: {{^}}name: vop2_instructions
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140
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141 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec
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221
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142 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec
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143 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit $mode, implicit $exec
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144 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F32_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit $mode, implicit $exec
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145 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F16_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit $mode, implicit $exec
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150
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146
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147 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec
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221
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148 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec
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149 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $mode, implicit $exec
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150 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F32_e64 0, 23, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit $mode, implicit $exec
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151 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F16_e64 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit $mode, implicit $exec
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150
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152
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221
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153 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec
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154 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $mode, implicit $exec
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155 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F32_e64 1, 23, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, 0, implicit $mode, implicit $exec
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156 # GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F16_e64 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 2, implicit $mode, implicit $exec
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150
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157
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158 name: vop2_instructions
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159 tracksRegLiveness: true
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160 registers:
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161 - { id: 0, class: vreg_64 }
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162 - { id: 1, class: vreg_64 }
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163 - { id: 2, class: sreg_64 }
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164 - { id: 3, class: vgpr_32 }
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165 - { id: 4, class: sreg_32_xm0 }
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166 - { id: 5, class: sreg_32_xm0 }
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167 - { id: 6, class: sreg_32_xm0 }
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168 - { id: 7, class: sreg_32_xm0 }
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169 - { id: 8, class: sreg_32 }
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170 - { id: 9, class: vgpr_32 }
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171 - { id: 10, class: vgpr_32 }
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172 - { id: 11, class: vgpr_32 }
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173 - { id: 12, class: vgpr_32 }
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174 - { id: 13, class: vgpr_32 }
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175 - { id: 14, class: vgpr_32 }
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176 - { id: 15, class: vgpr_32 }
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177 - { id: 16, class: vgpr_32 }
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178 - { id: 17, class: vgpr_32 }
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179 - { id: 18, class: vgpr_32 }
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180 - { id: 19, class: vgpr_32 }
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181 - { id: 20, class: vgpr_32 }
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182 - { id: 21, class: vgpr_32 }
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183 - { id: 22, class: vgpr_32 }
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184 - { id: 23, class: vgpr_32 }
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185 - { id: 24, class: vgpr_32 }
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186 - { id: 25, class: vgpr_32 }
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187 - { id: 26, class: vgpr_32 }
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188 - { id: 27, class: vgpr_32 }
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189 - { id: 28, class: vgpr_32 }
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190 - { id: 29, class: vgpr_32 }
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191 - { id: 30, class: vgpr_32 }
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192 - { id: 31, class: vgpr_32 }
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193 - { id: 32, class: vgpr_32 }
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194 - { id: 33, class: vgpr_32 }
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195 - { id: 34, class: vgpr_32 }
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196 - { id: 35, class: vgpr_32 }
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197 - { id: 36, class: vgpr_32 }
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198 - { id: 37, class: vgpr_32 }
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199 - { id: 38, class: vgpr_32 }
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200 - { id: 39, class: vgpr_32 }
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201 - { id: 40, class: vgpr_32 }
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202 - { id: 41, class: vgpr_32 }
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203 - { id: 42, class: vgpr_32 }
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204 - { id: 43, class: vgpr_32 }
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205 - { id: 44, class: vgpr_32 }
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206 - { id: 45, class: vgpr_32 }
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207 - { id: 46, class: vgpr_32 }
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208 - { id: 47, class: vgpr_32 }
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209 - { id: 48, class: vgpr_32 }
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210 - { id: 49, class: vgpr_32 }
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211 - { id: 50, class: vgpr_32 }
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212 - { id: 51, class: vgpr_32 }
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213 - { id: 52, class: vgpr_32 }
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214 - { id: 53, class: vgpr_32 }
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215 - { id: 54, class: vgpr_32 }
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216 - { id: 55, class: vgpr_32 }
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217 - { id: 56, class: vgpr_32 }
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218 - { id: 57, class: vgpr_32 }
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219 - { id: 58, class: vgpr_32 }
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220 - { id: 59, class: vgpr_32 }
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221 - { id: 60, class: vgpr_32 }
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222 - { id: 100, class: vgpr_32 }
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223 body: |
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224 bb.0:
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225 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
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226
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227 %2 = COPY $sgpr30_sgpr31
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228 %1 = COPY $vgpr2_vgpr3
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229 %0 = COPY $vgpr0_vgpr1
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223
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230 %3 = FLAT_LOAD_DWORD %1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))
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150
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231
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232 %5 = S_MOV_B32 65535
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233 %6 = S_MOV_B32 65535
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234
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235 %11 = V_LSHRREV_B32_e64 16, %3, implicit $exec
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236 %12 = V_AND_B32_e32 %6, %11, implicit $exec
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237 %13 = V_LSHLREV_B32_e64 16, %12, implicit $exec
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238 %14 = V_LSHRREV_B32_e64 16, %13, implicit $exec
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221
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239 %15 = V_BFE_U32_e64 %13, 8, 8, implicit $exec
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240 %16 = V_ADD_F32_e32 %14, %15, implicit $mode, implicit $exec
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150
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241 %17 = V_LSHLREV_B32_e64 16, %16, implicit $exec
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242 %18 = V_LSHRREV_B32_e64 16, %17, implicit $exec
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221
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243 %19 = V_BFE_U32_e64 %17, 8, 8, implicit $exec
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244 %20 = V_SUB_F16_e32 %18, %19, implicit $mode, implicit $exec
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150
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245 %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec
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221
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246 %22 = V_BFE_U32_e64 %20, 8, 8, implicit $exec
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247 %23 = V_FMAC_F32_e32 %21, %22, %22, implicit $mode, implicit $exec
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150
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248 %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec
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|
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249 %25 = V_LSHRREV_B32_e64 16, %24, implicit $exec
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221
|
250 %26 = V_BFE_U32_e64 %24, 8, 8, implicit $exec
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251 %27 = V_FMAC_F16_e32 %25, %26, %26, implicit $mode, implicit $exec
|
|
150
|
252 %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec
|
|
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253
|
|
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254 %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec
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|
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255 %30 = V_AND_B32_e64 23, %29, implicit $exec
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|
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256 %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec
|
|
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257 %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec
|
|
221
|
258 %33 = V_BFE_U32_e64 %31, 8, 8, implicit $exec
|
|
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259 %34 = V_ADD_F32_e64 0, %32, 0, %33, 0, 0, implicit $mode, implicit $exec
|
|
150
|
260 %35 = V_LSHLREV_B32_e64 16, %34, implicit $exec
|
|
221
|
261 %37 = V_BFE_U32_e64 %35, 8, 8, implicit $exec
|
|
|
262 %38 = V_SUB_F16_e64 0, 23, 0, %37, 0, 0, implicit $mode, implicit $exec
|
|
150
|
263 %39 = V_LSHLREV_B32_e64 16, %38, implicit $exec
|
|
221
|
264 %40 = V_BFE_U32_e64 %39, 8, 8, implicit $exec
|
|
|
265 %41 = V_FMAC_F32_e64 0, 23, 0, %40, 0, %40, 0, 0, implicit $mode, implicit $exec
|
|
150
|
266 %42 = V_LSHLREV_B32_e64 16, %41, implicit $exec
|
|
|
267 %43 = V_LSHRREV_B32_e64 16, %42, implicit $exec
|
|
221
|
268 %44 = V_BFE_U32_e64 %42, 8, 8, implicit $exec
|
|
|
269 %45 = V_FMAC_F16_e64 0, %43, 0, %44, 0, %44, 0, 0, implicit $mode, implicit $exec
|
|
150
|
270 %46 = V_LSHLREV_B32_e64 16, %45, implicit $exec
|
|
|
271
|
|
|
272 %47 = V_LSHRREV_B32_e64 16, %46, implicit $exec
|
|
221
|
273 %48 = V_BFE_U32_e64 %46, 8, 8, implicit $exec
|
|
|
274 %49 = V_ADD_F32_e64 0, %47, 1, %48, 0, 0, implicit $mode, implicit $exec
|
|
150
|
275 %50 = V_LSHLREV_B32_e64 16, %49, implicit $exec
|
|
221
|
276 %51 = V_BFE_U32_e64 %50, 8, 8, implicit $exec
|
|
|
277 %52 = V_SUB_F16_e64 1, 23, 1, %51, 0, 0, implicit $mode, implicit $exec
|
|
150
|
278 %53 = V_LSHLREV_B32_e64 16, %52, implicit $exec
|
|
221
|
279 %54 = V_BFE_U32_e64 %53, 8, 8, implicit $exec
|
|
|
280 %55 = V_FMAC_F32_e64 1, 23, 1, %54, 1, %54, 1, 0, implicit $mode, implicit $exec
|
|
150
|
281 %56 = V_LSHLREV_B32_e64 16, %55, implicit $exec
|
|
|
282 %57 = V_LSHRREV_B32_e64 16, %56, implicit $exec
|
|
221
|
283 %58 = V_BFE_U32_e64 %56, 8, 8, implicit $exec
|
|
|
284 %59 = V_FMAC_F16_e64 1, %57, 1, %58, 1, %58, 0, 2, implicit $mode, implicit $exec
|
|
150
|
285 %60 = V_LSHLREV_B32_e64 16, %59, implicit $exec
|
|
|
286
|
|
|
287 %100 = V_MOV_B32_e32 %60, implicit $exec
|
|
|
288
|
|
223
|
289 FLAT_STORE_DWORD %0, %100, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))
|
|
150
|
290 $sgpr30_sgpr31 = COPY %2
|
|
|
291 S_SETPC_B64_return $sgpr30_sgpr31
|
|
|
292
|
|
|
293 ...
|
