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annotate lib/Target/Sparc/SparcISelLowering.h @ 83:60c9769439b8 LLVM3.7

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children afa8332a0e37
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1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
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11 // selection DAG.
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12 //
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13 //===----------------------------------------------------------------------===//
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15 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
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16 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
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17
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18 #include "Sparc.h"
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19 #include "llvm/Target/TargetLowering.h"
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20
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21 namespace llvm {
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22 class SparcSubtarget;
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23
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24 namespace SPISD {
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25 enum {
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26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
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27 CMPICC, // Compare two GPR operands, set icc+xcc.
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28 CMPFCC, // Compare two FP operands, set fcc.
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29 BRICC, // Branch to dest on icc condition
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30 BRXCC, // Branch to dest on xcc condition (64-bit only).
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31 BRFCC, // Branch to dest on fcc condition
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32 SELECT_ICC, // Select between two values using the current ICC flags.
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33 SELECT_XCC, // Select between two values using the current XCC flags.
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34 SELECT_FCC, // Select between two values using the current FCC flags.
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35
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36 Hi, Lo, // Hi/Lo operations, typically on a global address.
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37
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38 FTOI, // FP to Int within a FP register.
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39 ITOF, // Int to FP within a FP register.
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40 FTOX, // FP to Int64 within a FP register.
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41 XTOF, // Int64 to FP within a FP register.
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42
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43 CALL, // A call instruction.
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44 RET_FLAG, // Return with a flag operand.
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45 GLOBAL_BASE_REG, // Global base reg for PIC.
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46 FLUSHW, // FLUSH register windows to stack.
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47
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48 TLS_ADD, // For Thread Local Storage (TLS).
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49 TLS_LD,
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50 TLS_CALL
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51 };
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52 }
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53
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54 class SparcTargetLowering : public TargetLowering {
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55 const SparcSubtarget *Subtarget;
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56 public:
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57 SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI);
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58 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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59
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60 /// computeKnownBitsForTargetNode - Determine which of the bits specified
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61 /// in Mask are known to be either zero or one and return them in the
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62 /// KnownZero/KnownOne bitsets.
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63 void computeKnownBitsForTargetNode(const SDValue Op,
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64 APInt &KnownZero,
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65 APInt &KnownOne,
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66 const SelectionDAG &DAG,
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67 unsigned Depth = 0) const override;
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68
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69 MachineBasicBlock *
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70 EmitInstrWithCustomInserter(MachineInstr *MI,
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71 MachineBasicBlock *MBB) const override;
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72
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73 const char *getTargetNodeName(unsigned Opcode) const override;
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74
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75 ConstraintType getConstraintType(const std::string &Constraint) const override;
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76 ConstraintWeight
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77 getSingleConstraintMatchWeight(AsmOperandInfo &info,
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78 const char *constraint) const override;
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79 void LowerAsmOperandForConstraint(SDValue Op,
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80 std::string &Constraint,
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81 std::vector<SDValue> &Ops,
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82 SelectionDAG &DAG) const override;
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83 std::pair<unsigned, const TargetRegisterClass*>
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84 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const override;
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85
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86 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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87 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
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89 /// getSetCCResultType - Return the ISD::SETCC ValueType
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90 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
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91
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92 SDValue
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93 LowerFormalArguments(SDValue Chain,
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94 CallingConv::ID CallConv,
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95 bool isVarArg,
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96 const SmallVectorImpl<ISD::InputArg> &Ins,
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97 SDLoc dl, SelectionDAG &DAG,
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98 SmallVectorImpl<SDValue> &InVals) const override;
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99 SDValue LowerFormalArguments_32(SDValue Chain,
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100 CallingConv::ID CallConv,
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101 bool isVarArg,
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102 const SmallVectorImpl<ISD::InputArg> &Ins,
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103 SDLoc dl, SelectionDAG &DAG,
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104 SmallVectorImpl<SDValue> &InVals) const;
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105 SDValue LowerFormalArguments_64(SDValue Chain,
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106 CallingConv::ID CallConv,
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107 bool isVarArg,
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108 const SmallVectorImpl<ISD::InputArg> &Ins,
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109 SDLoc dl, SelectionDAG &DAG,
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110 SmallVectorImpl<SDValue> &InVals) const;
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111
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112 SDValue
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113 LowerCall(TargetLowering::CallLoweringInfo &CLI,
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114 SmallVectorImpl<SDValue> &InVals) const override;
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115 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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116 SmallVectorImpl<SDValue> &InVals) const;
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117 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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118 SmallVectorImpl<SDValue> &InVals) const;
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119
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120 SDValue
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121 LowerReturn(SDValue Chain,
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122 CallingConv::ID CallConv, bool isVarArg,
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123 const SmallVectorImpl<ISD::OutputArg> &Outs,
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124 const SmallVectorImpl<SDValue> &OutVals,
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125 SDLoc dl, SelectionDAG &DAG) const override;
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126 SDValue LowerReturn_32(SDValue Chain,
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127 CallingConv::ID CallConv, bool IsVarArg,
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128 const SmallVectorImpl<ISD::OutputArg> &Outs,
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129 const SmallVectorImpl<SDValue> &OutVals,
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130 SDLoc DL, SelectionDAG &DAG) const;
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131 SDValue LowerReturn_64(SDValue Chain,
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132 CallingConv::ID CallConv, bool IsVarArg,
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133 const SmallVectorImpl<ISD::OutputArg> &Outs,
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134 const SmallVectorImpl<SDValue> &OutVals,
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135 SDLoc DL, SelectionDAG &DAG) const;
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136
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137 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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138 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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139 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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140 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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141
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142 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
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143 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
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144 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
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145 SelectionDAG &DAG) const;
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146 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
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147
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148 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
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149 SDValue Arg, SDLoc DL,
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150 SelectionDAG &DAG) const;
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151 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
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152 const char *LibFuncName,
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153 unsigned numArgs) const;
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154 SDValue LowerF128Compare(SDValue LHS, SDValue RHS,
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155 unsigned &SPCC,
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156 SDLoc DL,
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157 SelectionDAG &DAG) const;
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158
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159 bool ShouldShrinkFPConstant(EVT VT) const override {
0
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160 // Do not shrink FP constpool if VT == MVT::f128.
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161 // (ldd, call _Q_fdtoq) is more expensive than two ldds.
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162 return VT != MVT::f128;
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163 }
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164
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165 void ReplaceNodeResults(SDNode *N,
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166 SmallVectorImpl<SDValue>& Results,
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167 SelectionDAG &DAG) const override;
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168
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169 MachineBasicBlock *expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB,
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170 unsigned BROpcode) const;
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171 MachineBasicBlock *expandAtomicRMW(MachineInstr *MI,
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172 MachineBasicBlock *BB,
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173 unsigned Opcode,
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174 unsigned CondCode = 0) const;
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175 };
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176 } // end namespace llvm
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177
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178 #endif // SPARC_ISELLOWERING_H