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1 ; Check the miscellaneous logical vector operations added in P8
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2 ;
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3 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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4 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
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5 ; Test x eqv y
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6 define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
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7 %tmp = xor <4 x i32> %x, %y
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8 %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
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9 ret <4 x i32> %ret_val
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10 ; CHECK: veqv 2, 2, 3
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11 }
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12
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13 ; Test x vnand y
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14 define <4 x i32> @test_vnand(<4 x i32> %x, <4 x i32> %y) nounwind {
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15 %tmp = and <4 x i32> %x, %y
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16 %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
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17 ret <4 x i32> %ret_val
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18 ; CHECK: vnand 2, 2, 3
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19 }
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20
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21 ; Test x vorc y
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22 define <4 x i32> @test_vorc(<4 x i32> %x, <4 x i32> %y) nounwind {
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23 %tmp = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
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24 %ret_val = or <4 x i32> %x, %tmp
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25 ret <4 x i32> %ret_val
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26 ; CHECK: vorc 2, 2, 3
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27 }
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