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annotate test/CodeGen/X86/sse4a.ll @ 83:60c9769439b8 LLVM3.7

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 95c75e76d11b
children 1172e4bd9c6f
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1 ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s
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2 ; RUN: llc < %s -mtriple=x86_64-unknown-linux -mattr=sse4a | FileCheck %s
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4 define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp {
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5 ; CHECK-LABEL: test1:
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6 ; CHECK: movntss
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7 tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) nounwind
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8 ret void
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9 }
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11 declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>)
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13 define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp {
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14 ; CHECK-LABEL: test2:
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15 ; CHECK: movntsd
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16 tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a) nounwind
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17 ret void
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18 }
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20 declare void @llvm.x86.sse4a.movnt.sd(i8*, <2 x double>)
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21
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22 define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp {
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23 ; CHECK-LABEL: test3:
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24 ; CHECK: extrq
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25 %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)
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26 ret <2 x i64> %1
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27 }
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29 declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
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31 define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
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32 ; CHECK-LABEL: test4:
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33 ; CHECK: extrq
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34 %1 = bitcast <2 x i64> %y to <16 x i8>
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35 %2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind
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36 ret <2 x i64> %2
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37 }
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39 declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
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41 define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
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42 ; CHECK-LABEL: test5:
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43 ; CHECK: insertq
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44 %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)
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45 ret <2 x i64> %1
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46 }
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48 declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
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50 define <2 x i64> @test6(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
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51 ; CHECK-LABEL: test6:
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52 ; CHECK: insertq
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53 %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
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54 ret <2 x i64> %1
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55 }
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57 declare <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64>, <2 x i64>) nounwind