annotate test/CodeGen/X86/vec_fneg.ll @ 83:60c9769439b8 LLVM3.7

LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children 1172e4bd9c6f
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse | FileCheck %s
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2
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3 ; FNEG is defined as subtraction from -0.0.
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4
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5 ; This test verifies that we use an xor with a constant to flip the sign bits; no subtraction needed.
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6 define <4 x float> @t1(<4 x float> %Q) {
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7 ; CHECK-LABEL: t1:
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8 ; CHECK: xorps {{.*}}LCPI0_0{{.*}}, %xmm0
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9 ; CHECK-NEXT: retq
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10 %tmp = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %Q
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11 ret <4 x float> %tmp
0
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12 }
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14 ; This test verifies that we generate an FP subtraction because "0.0 - x" is not an fneg.
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15 define <4 x float> @t2(<4 x float> %Q) {
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16 ; CHECK-LABEL: t2:
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17 ; CHECK: xorps %[[X:xmm[0-9]+]], %[[X]]
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18 ; CHECK-NEXT: subps %xmm0, %[[X]]
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19 ; CHECK-NEXT: movaps %[[X]], %xmm0
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20 ; CHECK-NEXT: retq
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21 %tmp = fsub <4 x float> zeroinitializer, %Q
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22 ret <4 x float> %tmp
0
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23 }
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24
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25 ; If we're bitcasting an integer to an FP vector, we should avoid the FPU/vector unit entirely.
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26 ; Make sure that we're flipping the sign bit and only the sign bit of each float.
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27 ; So instead of something like this:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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28 ; movd %rdi, %xmm0
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29 ; xorps .LCPI2_0(%rip), %xmm0
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30 ;
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31 ; We should generate:
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32 ; movabsq (put sign bit mask in integer register))
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33 ; xorq (flip sign bits)
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34 ; movd (move to xmm return register)
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35
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36 define <2 x float> @fneg_bitcast(i64 %i) {
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37 ; CHECK-LABEL: fneg_bitcast:
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38 ; CHECK: movabsq $-9223372034707292160, %rax # imm = 0x8000000080000000
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39 ; CHECK-NEXT: xorq %rdi, %rax
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40 ; CHECK-NEXT: movd %rax, %xmm0
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41 ; CHECK-NEXT: retq
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42 %bitcast = bitcast i64 %i to <2 x float>
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43 %fneg = fsub <2 x float> <float -0.0, float -0.0>, %bitcast
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44 ret <2 x float> %fneg
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45 }