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1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
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2 //
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147
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 //
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10 //===----------------------------------------------------------------------===//
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11
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12 #include "SparcTargetMachine.h"
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13 #include "LeonPasses.h"
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14 #include "Sparc.h"
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15 #include "SparcTargetObjectFile.h"
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16 #include "TargetInfo/SparcTargetInfo.h"
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17 #include "llvm/CodeGen/Passes.h"
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18 #include "llvm/CodeGen/TargetPassConfig.h"
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19 #include "llvm/IR/LegacyPassManager.h"
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20 #include "llvm/Support/TargetRegistry.h"
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21 using namespace llvm;
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22
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23 extern "C" void LLVMInitializeSparcTarget() {
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24 // Register the target.
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25 RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
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26 RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
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27 RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
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28 }
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29
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30 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
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31 // Sparc is typically big endian, but some are little.
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32 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
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33 Ret += "-m:e";
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34
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35 // Some ABIs have 32bit pointers.
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36 if (!is64Bit)
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37 Ret += "-p:32:32";
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38
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39 // Alignments for 64 bit integers.
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40 Ret += "-i64:64";
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41
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42 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
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43 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
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44 if (is64Bit)
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45 Ret += "-n32:64";
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46 else
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47 Ret += "-f128:64-n32";
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48
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49 if (is64Bit)
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50 Ret += "-S128";
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51 else
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52 Ret += "-S64";
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53
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54 return Ret;
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55 }
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56
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57 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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58 if (!RM.hasValue())
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59 return Reloc::Static;
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60 return *RM;
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61 }
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62
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63 // Code models. Some only make sense for 64-bit code.
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64 //
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65 // SunCC Reloc CodeModel Constraints
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66 // abs32 Static Small text+data+bss linked below 2^32 bytes
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67 // abs44 Static Medium text+data+bss linked below 2^44 bytes
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68 // abs64 Static Large text smaller than 2^31 bytes
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69 // pic13 PIC_ Small GOT < 2^13 bytes
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70 // pic32 PIC_ Medium GOT < 2^32 bytes
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71 //
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72 // All code models require that the text segment is smaller than 2GB.
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73 static CodeModel::Model
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74 getEffectiveSparcCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM,
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75 bool Is64Bit, bool JIT) {
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76 if (CM) {
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77 if (*CM == CodeModel::Tiny)
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78 report_fatal_error("Target does not support the tiny CodeModel", false);
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79 if (*CM == CodeModel::Kernel)
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80 report_fatal_error("Target does not support the kernel CodeModel", false);
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121
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81 return *CM;
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82 }
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83 if (Is64Bit) {
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84 if (JIT)
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85 return CodeModel::Large;
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86 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
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87 }
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88 return CodeModel::Small;
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89 }
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90
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91 /// Create an ILP32 architecture model
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92 SparcTargetMachine::SparcTargetMachine(
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93 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
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94 const TargetOptions &Options, Optional<Reloc::Model> RM,
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95 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
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96 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
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97 getEffectiveRelocModel(RM),
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98 getEffectiveSparcCodeModel(
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99 CM, getEffectiveRelocModel(RM), is64bit, JIT),
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100 OL),
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101 TLOF(make_unique<SparcELFTargetObjectFile>()),
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102 Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
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103 initAsmInfo();
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104 }
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105
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106 SparcTargetMachine::~SparcTargetMachine() {}
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107
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108 const SparcSubtarget *
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109 SparcTargetMachine::getSubtargetImpl(const Function &F) const {
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110 Attribute CPUAttr = F.getFnAttribute("target-cpu");
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111 Attribute FSAttr = F.getFnAttribute("target-features");
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112
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113 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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114 ? CPUAttr.getValueAsString().str()
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115 : TargetCPU;
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116 std::string FS = !FSAttr.hasAttribute(Attribute::None)
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117 ? FSAttr.getValueAsString().str()
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118 : TargetFS;
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119
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120 // FIXME: This is related to the code below to reset the target options,
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121 // we need to know whether or not the soft float flag is set on the
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122 // function, so we can enable it as a subtarget feature.
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123 bool softFloat =
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124 F.hasFnAttribute("use-soft-float") &&
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125 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
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126
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127 if (softFloat)
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128 FS += FS.empty() ? "+soft-float" : ",+soft-float";
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129
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130 auto &I = SubtargetMap[CPU + FS];
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131 if (!I) {
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132 // This needs to be done before we create a new subtarget since any
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133 // creation will depend on the TM and the code generation flags on the
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134 // function that reside in TargetOptions.
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135 resetTargetOptions(F);
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136 I = llvm::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this,
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137 this->is64Bit);
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138 }
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139 return I.get();
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140 }
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141
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142 namespace {
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143 /// Sparc Code Generator Pass Configuration Options.
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144 class SparcPassConfig : public TargetPassConfig {
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145 public:
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146 SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM)
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147 : TargetPassConfig(TM, PM) {}
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148
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149 SparcTargetMachine &getSparcTargetMachine() const {
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150 return getTM<SparcTargetMachine>();
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151 }
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152
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153 void addIRPasses() override;
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154 bool addInstSelector() override;
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155 void addPreEmitPass() override;
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156 };
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157 } // namespace
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158
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159 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
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160 return new SparcPassConfig(*this, PM);
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161 }
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162
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163 void SparcPassConfig::addIRPasses() {
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164 addPass(createAtomicExpandPass());
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165
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166 TargetPassConfig::addIRPasses();
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167 }
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168
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169 bool SparcPassConfig::addInstSelector() {
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170 addPass(createSparcISelDag(getSparcTargetMachine()));
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171 return false;
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172 }
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173
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174 void SparcPassConfig::addPreEmitPass(){
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175 addPass(createSparcDelaySlotFillerPass());
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176
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177 if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
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178 {
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179 addPass(new InsertNOPLoad());
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120
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180 }
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181 if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) {
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182 addPass(new DetectRoundChange());
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183 }
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184 if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
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185 {
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186 addPass(new FixAllFDIVSQRT());
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187 }
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188 }
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189
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190 void SparcV8TargetMachine::anchor() { }
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191
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192 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
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193 StringRef CPU, StringRef FS,
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194 const TargetOptions &Options,
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195 Optional<Reloc::Model> RM,
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196 Optional<CodeModel::Model> CM,
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197 CodeGenOpt::Level OL, bool JIT)
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198 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
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199
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200 void SparcV9TargetMachine::anchor() { }
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201
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202 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
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203 StringRef CPU, StringRef FS,
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204 const TargetOptions &Options,
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205 Optional<Reloc::Model> RM,
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206 Optional<CodeModel::Model> CM,
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207 CodeGenOpt::Level OL, bool JIT)
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208 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
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209
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210 void SparcelTargetMachine::anchor() {}
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211
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212 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
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213 StringRef CPU, StringRef FS,
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214 const TargetOptions &Options,
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215 Optional<Reloc::Model> RM,
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216 Optional<CodeModel::Model> CM,
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217 CodeGenOpt::Level OL, bool JIT)
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218 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
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