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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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221
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2 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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3 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
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150
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4
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5 define amdgpu_ps float @main(float %arg0, float %arg1) #0 {
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6 ; SI-LABEL: main:
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7 ; SI: ; %bb.0: ; %bb
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8 ; SI-NEXT: v_cvt_i32_f32_e32 v0, v0
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9 ; SI-NEXT: s_mov_b32 s0, 0
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10 ; SI-NEXT: s_mov_b32 s1, s0
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11 ; SI-NEXT: s_mov_b32 s2, s0
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12 ; SI-NEXT: s_mov_b32 s3, s0
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13 ; SI-NEXT: s_mov_b32 s4, s0
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14 ; SI-NEXT: s_mov_b32 s5, s0
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15 ; SI-NEXT: s_mov_b32 s6, s0
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16 ; SI-NEXT: s_mov_b32 s7, s0
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17 ; SI-NEXT: image_load v2, v0, s[0:7] dmask:0x1 unorm
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18 ; SI-NEXT: v_and_b32_e32 v0, 7, v0
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19 ; SI-NEXT: s_waitcnt vmcnt(0)
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20 ; SI-NEXT: v_lshr_b32_e32 v0, v2, v0
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21 ; SI-NEXT: v_and_b32_e32 v0, 1, v0
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22 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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23 ; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
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24 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v0, s0, v0
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25 ; SI-NEXT: ; return to shader part epilog
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26 ;
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27 ; VI-LABEL: main:
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28 ; VI: ; %bb.0: ; %bb
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29 ; VI-NEXT: v_cvt_i32_f32_e32 v0, v0
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30 ; VI-NEXT: s_mov_b32 s0, 0
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31 ; VI-NEXT: s_mov_b32 s1, s0
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32 ; VI-NEXT: s_mov_b32 s2, s0
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33 ; VI-NEXT: s_mov_b32 s3, s0
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34 ; VI-NEXT: s_mov_b32 s4, s0
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35 ; VI-NEXT: s_mov_b32 s5, s0
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36 ; VI-NEXT: s_mov_b32 s6, s0
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37 ; VI-NEXT: s_mov_b32 s7, s0
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38 ; VI-NEXT: image_load v2, v0, s[0:7] dmask:0x1 unorm
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39 ; VI-NEXT: v_and_b32_e32 v0, 7, v0
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40 ; VI-NEXT: s_waitcnt vmcnt(0)
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41 ; VI-NEXT: v_lshrrev_b32_e32 v0, v0, v2
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42 ; VI-NEXT: v_and_b32_e32 v0, 1, v0
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43 ; VI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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44 ; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
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45 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, s0, v0
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46 ; VI-NEXT: ; return to shader part epilog
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47 bb:
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48 %tmp = fptosi float %arg0 to i32
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49 %tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 undef, <8 x i32> undef, i32 0, i32 0)
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50 %tmp2.f = extractelement <4 x float> %tmp1, i32 0
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51 %tmp2 = bitcast float %tmp2.f to i32
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52 %tmp3 = and i32 %tmp, 7
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53 %tmp4 = shl i32 1, %tmp3
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54 %tmp5 = and i32 %tmp2, %tmp4
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55 %tmp6 = icmp eq i32 %tmp5, 0
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56 %tmp7 = select i1 %tmp6, float 0.000000e+00, float %arg1
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57 %tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp7)
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58 %tmp9 = bitcast <2 x half> %tmp8 to float
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59 ret float %tmp9
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60 }
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61
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62 declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
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63 declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #2
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64
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65 attributes #0 = { nounwind }
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66 attributes #1 = { nounwind readnone }
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67 attributes #2 = { nounwind readonly }
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