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221
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI-SAFE,GCN,FUNC %s
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2 ; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN-NONAN,GCN,FUNC %s
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150
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3
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221
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4 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI-SAFE,GCN,FUNC %s
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5 ; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN-NONAN,GCN,FUNC %s
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150
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6
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221
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7 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope --check-prefixes=EG,FUNC %s
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150
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8
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9 declare i32 @llvm.amdgcn.workitem.id.x() #1
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10
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11 ; FUNC-LABEL: {{^}}test_fmax_legacy_uge_f32:
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12 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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13 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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14
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15 ; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
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16
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17 ; VI-SAFE: v_cmp_nlt_f32_e32 vcc, [[A]], [[B]]
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18 ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
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19
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20 ; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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21
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22 ; EG: MAX
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23 define amdgpu_kernel void @test_fmax_legacy_uge_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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24 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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25 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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26 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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27
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28 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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29 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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30
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31 %cmp = fcmp uge float %a, %b
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32 %val = select i1 %cmp, float %a, float %b
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33 store float %val, float addrspace(1)* %out, align 4
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34 ret void
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35 }
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36
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37 ; FUNC-LABEL: {{^}}test_fmax_legacy_uge_f32_nnan_src:
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38 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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39 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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40 ; GCN-DAG: v_add_f32_e32 [[ADD_A:v[0-9]+]], 1.0, [[A]]
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41 ; GCN-DAG: v_add_f32_e32 [[ADD_B:v[0-9]+]], 2.0, [[B]]
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42
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43 ; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]
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44
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45 ; VI-SAFE: v_cmp_nlt_f32_e32 vcc, [[ADD_A]], [[ADD_B]]
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46 ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[ADD_B]], [[ADD_A]]
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47
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48 ; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]
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49
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50 ; EG: MAX
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51 define amdgpu_kernel void @test_fmax_legacy_uge_f32_nnan_src(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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52 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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53 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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54 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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55
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56 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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57 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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58 %a.nnan = fadd nnan float %a, 1.0
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59 %b.nnan = fadd nnan float %b, 2.0
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60
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61 %cmp = fcmp uge float %a.nnan, %b.nnan
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62 %val = select i1 %cmp, float %a.nnan, float %b.nnan
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63 store float %val, float addrspace(1)* %out, align 4
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64 ret void
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65 }
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66
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67 ; FUNC-LABEL: {{^}}test_fmax_legacy_oge_f32:
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68 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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69 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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70
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71 ; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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72
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73 ; VI-SAFE: v_cmp_ge_f32_e32 vcc, [[A]], [[B]]
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74 ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
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75
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76 ; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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77 ; EG: MAX
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78 define amdgpu_kernel void @test_fmax_legacy_oge_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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79 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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80 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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81 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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82
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83 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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84 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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85
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86 %cmp = fcmp oge float %a, %b
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87 %val = select i1 %cmp, float %a, float %b
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88 store float %val, float addrspace(1)* %out, align 4
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89 ret void
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90 }
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91
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92 ; FUNC-LABEL: {{^}}test_fmax_legacy_ugt_f32:
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93 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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94 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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95
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96 ; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
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97
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98 ; VI-SAFE: v_cmp_nle_f32_e32 vcc, [[A]], [[B]]
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99 ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
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100
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101
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102 ; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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103 ; EG: MAX
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104 define amdgpu_kernel void @test_fmax_legacy_ugt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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105 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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106 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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107 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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108
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109 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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110 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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111
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112 %cmp = fcmp ugt float %a, %b
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113 %val = select i1 %cmp, float %a, float %b
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114 store float %val, float addrspace(1)* %out, align 4
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115 ret void
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116 }
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117
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118 ; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_f32:
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119 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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120 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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121
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122 ; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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123
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124 ; VI-SAFE: v_cmp_gt_f32_e32 vcc, [[A]], [[B]]
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125 ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
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126
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127 ; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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128 ; EG: MAX
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129 define amdgpu_kernel void @test_fmax_legacy_ogt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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130 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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131 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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132 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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133
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134 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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135 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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136
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137 %cmp = fcmp ogt float %a, %b
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138 %val = select i1 %cmp, float %a, float %b
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139 store float %val, float addrspace(1)* %out, align 4
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140 ret void
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141 }
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142
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143 ; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v1f32:
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144 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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145 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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146
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147 ; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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148
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149 ; VI-SAFE: v_cmp_gt_f32_e32 vcc, [[A]], [[B]]
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150 ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
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151
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152
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153 ; GCN-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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154 ; EG: MAX
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155 define amdgpu_kernel void @test_fmax_legacy_ogt_v1f32(<1 x float> addrspace(1)* %out, <1 x float> addrspace(1)* %in) #0 {
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156 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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157 %gep.0 = getelementptr <1 x float>, <1 x float> addrspace(1)* %in, i32 %tid
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158 %gep.1 = getelementptr <1 x float>, <1 x float> addrspace(1)* %gep.0, i32 1
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159
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160 %a = load <1 x float>, <1 x float> addrspace(1)* %gep.0
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161 %b = load <1 x float>, <1 x float> addrspace(1)* %gep.1
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162
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163 %cmp = fcmp ogt <1 x float> %a, %b
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164 %val = select <1 x i1> %cmp, <1 x float> %a, <1 x float> %b
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165 store <1 x float> %val, <1 x float> addrspace(1)* %out
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166 ret void
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167 }
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168
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169 ; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v3f32:
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170 ; SI-SAFE: v_max_legacy_f32_e32
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171 ; SI-SAFE: v_max_legacy_f32_e32
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172 ; SI-SAFE: v_max_legacy_f32_e32
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173
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174 ; VI-SAFE: v_cmp_gt_f32_e32
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175 ; VI-SAFE: v_cndmask_b32_e32
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176 ; VI-SAFE: v_cmp_gt_f32_e32
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177 ; VI-SAFE: v_cndmask_b32_e32
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178 ; VI-SAFE: v_cmp_gt_f32_e32
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179 ; VI-SAFE: v_cndmask_b32_e32
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180 ; VI-SAFE-NOT: v_cmp
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181 ; VI-SAFE-NOT: v_cndmask
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182
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183 ; GCN-NONAN: v_max_f32_e32
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184 ; GCN-NONAN: v_max_f32_e32
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185 ; GCN-NONAN: v_max_f32_e32
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186
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187 ; GCN-NOT: v_max
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188 define amdgpu_kernel void @test_fmax_legacy_ogt_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %in) #0 {
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189 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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190 %gep.0 = getelementptr <3 x float>, <3 x float> addrspace(1)* %in, i32 %tid
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191 %gep.1 = getelementptr <3 x float>, <3 x float> addrspace(1)* %gep.0, i32 1
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192
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193 %a = load <3 x float>, <3 x float> addrspace(1)* %gep.0
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194 %b = load <3 x float>, <3 x float> addrspace(1)* %gep.1
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195
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196 %cmp = fcmp ogt <3 x float> %a, %b
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197 %val = select <3 x i1> %cmp, <3 x float> %a, <3 x float> %b
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198 store <3 x float> %val, <3 x float> addrspace(1)* %out
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199 ret void
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200 }
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201
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202 ; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_f32_multi_use:
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203 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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204 ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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205 ; GCN-NOT: v_max_
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206 ; GCN: v_cmp_gt_f32
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207 ; GCN-NEXT: v_cndmask_b32
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208 ; GCN-NOT: v_max_
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209
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210 ; EG: MAX
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211 define amdgpu_kernel void @test_fmax_legacy_ogt_f32_multi_use(float addrspace(1)* %out0, i1 addrspace(1)* %out1, float addrspace(1)* %in) #0 {
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212 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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213 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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214 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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215
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216 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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217 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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218
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219 %cmp = fcmp ogt float %a, %b
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220 %val = select i1 %cmp, float %a, float %b
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221 store float %val, float addrspace(1)* %out0, align 4
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222 store i1 %cmp, i1addrspace(1)* %out1
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223 ret void
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224 }
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225
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226 attributes #0 = { nounwind }
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227 attributes #1 = { nounwind readnone }
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