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221
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
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3 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -global-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10GISEL %s
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4 ; TODO: global-isel produces more code - there will need to be some more combines in the postregbankselectcombine phase
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5 ; Depends on some other changes to pass this test - those are in review separately
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6
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7 define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s) {
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8 ; GFX10-LABEL: sample_d_1d:
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9 ; GFX10: ; %bb.0: ; %main_body
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10 ; GFX10-NEXT: image_sample_d v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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11 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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12 ; GFX10-NEXT: ; return to shader part epilog
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13 ;
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14 ; GFX10GISEL-LABEL: sample_d_1d:
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15 ; GFX10GISEL: ; %bb.0: ; %main_body
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16 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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17 ; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, s12
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18 ; GFX10GISEL-NEXT: image_sample_d v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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19 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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20 ; GFX10GISEL-NEXT: ; return to shader part epilog
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21 main_body:
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22 %v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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23 ret <4 x float> %v
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24 }
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25
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26 define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) {
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27 ; GFX10-LABEL: sample_d_2d:
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28 ; GFX10: ; %bb.0: ; %main_body
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29 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v4
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30 ; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4
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31 ; GFX10-NEXT: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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32 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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33 ; GFX10-NEXT: ; return to shader part epilog
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34 ;
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35 ; GFX10GISEL-LABEL: sample_d_2d:
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36 ; GFX10GISEL: ; %bb.0: ; %main_body
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37 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
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38 ; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v4, v5
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39 ; GFX10GISEL-NEXT: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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40 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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41 ; GFX10GISEL-NEXT: ; return to shader part epilog
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42 main_body:
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43 %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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44 ret <4 x float> %v
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45 }
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46
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47 define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, half %s, half %t, half %r) {
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48 ; GFX10-LABEL: sample_d_3d:
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49 ; GFX10: ; %bb.0: ; %main_body
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50 ; GFX10-NEXT: v_and_b32_e32 v6, 0xffff, v6
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51 ; GFX10-NEXT: v_lshl_or_b32 v6, v7, 16, v6
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52 ; GFX10-NEXT: image_sample_d v[0:3], [v0, v1, v2, v3, v4, v5, v6, v8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
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53 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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54 ; GFX10-NEXT: ; return to shader part epilog
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55 ;
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56 ; GFX10GISEL-LABEL: sample_d_3d:
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57 ; GFX10GISEL: ; %bb.0: ; %main_body
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58 ; GFX10GISEL-NEXT: v_mov_b32_e32 v9, 0xffff
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59 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v7, 16, v7
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60 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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61 ; GFX10GISEL-NEXT: v_and_or_b32 v6, v6, v9, v7
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62 ; GFX10GISEL-NEXT: v_and_or_b32 v7, v8, v9, s12
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63 ; GFX10GISEL-NEXT: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
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64 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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65 ; GFX10GISEL-NEXT: ; return to shader part epilog
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66 main_body:
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67 %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, half %s, half %t, half %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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68 ret <4 x float> %v
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69 }
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70
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71 define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s) {
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72 ; GFX10-LABEL: sample_c_d_1d:
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73 ; GFX10: ; %bb.0: ; %main_body
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74 ; GFX10-NEXT: image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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75 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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76 ; GFX10-NEXT: ; return to shader part epilog
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77 ;
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78 ; GFX10GISEL-LABEL: sample_c_d_1d:
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79 ; GFX10GISEL: ; %bb.0: ; %main_body
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80 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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81 ; GFX10GISEL-NEXT: v_and_or_b32 v3, 0xffff, v3, s12
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82 ; GFX10GISEL-NEXT: image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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83 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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84 ; GFX10GISEL-NEXT: ; return to shader part epilog
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85 main_body:
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86 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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87 ret <4 x float> %v
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88 }
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89
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90 define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) {
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91 ; GFX10-LABEL: sample_c_d_2d:
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92 ; GFX10: ; %bb.0: ; %main_body
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93 ; GFX10-NEXT: v_and_b32_e32 v5, 0xffff, v5
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94 ; GFX10-NEXT: v_lshl_or_b32 v5, v6, 16, v5
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95 ; GFX10-NEXT: image_sample_c_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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96 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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97 ; GFX10-NEXT: ; return to shader part epilog
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98 ;
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99 ; GFX10GISEL-LABEL: sample_c_d_2d:
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100 ; GFX10GISEL: ; %bb.0: ; %main_body
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101 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
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102 ; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v5, v6
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103 ; GFX10GISEL-NEXT: image_sample_c_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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104 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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105 ; GFX10GISEL-NEXT: ; return to shader part epilog
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106 main_body:
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107 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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108 ret <4 x float> %v
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109 }
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110
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111 define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s, half %clamp) {
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112 ; GFX10-LABEL: sample_d_cl_1d:
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113 ; GFX10: ; %bb.0: ; %main_body
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114 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2
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115 ; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2
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116 ; GFX10-NEXT: image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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117 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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118 ; GFX10-NEXT: ; return to shader part epilog
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119 ;
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120 ; GFX10GISEL-LABEL: sample_d_cl_1d:
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121 ; GFX10GISEL: ; %bb.0: ; %main_body
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122 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
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123 ; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, v3
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124 ; GFX10GISEL-NEXT: image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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125 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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126 ; GFX10GISEL-NEXT: ; return to shader part epilog
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127 main_body:
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128 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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129 ret <4 x float> %v
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130 }
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131
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132 define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
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133 ; GFX10-LABEL: sample_d_cl_2d:
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134 ; GFX10: ; %bb.0: ; %main_body
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135 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v4
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136 ; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4
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137 ; GFX10-NEXT: image_sample_d_cl v[0:3], [v0, v1, v2, v3, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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138 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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139 ; GFX10-NEXT: ; return to shader part epilog
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140 ;
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141 ; GFX10GISEL-LABEL: sample_d_cl_2d:
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142 ; GFX10GISEL: ; %bb.0: ; %main_body
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143 ; GFX10GISEL-NEXT: v_mov_b32_e32 v7, 0xffff
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144 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
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145 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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146 ; GFX10GISEL-NEXT: v_and_or_b32 v4, v4, v7, v5
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147 ; GFX10GISEL-NEXT: v_and_or_b32 v5, v6, v7, s12
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148 ; GFX10GISEL-NEXT: image_sample_d_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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149 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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150 ; GFX10GISEL-NEXT: ; return to shader part epilog
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151 main_body:
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152 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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153 ret <4 x float> %v
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154 }
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155
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156 define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp) {
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157 ; GFX10-LABEL: sample_c_d_cl_1d:
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158 ; GFX10: ; %bb.0: ; %main_body
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159 ; GFX10-NEXT: v_and_b32_e32 v3, 0xffff, v3
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160 ; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3
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161 ; GFX10-NEXT: image_sample_c_d_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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162 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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163 ; GFX10-NEXT: ; return to shader part epilog
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164 ;
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165 ; GFX10GISEL-LABEL: sample_c_d_cl_1d:
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166 ; GFX10GISEL: ; %bb.0: ; %main_body
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167 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4
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168 ; GFX10GISEL-NEXT: v_and_or_b32 v3, 0xffff, v3, v4
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169 ; GFX10GISEL-NEXT: image_sample_c_d_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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170 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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171 ; GFX10GISEL-NEXT: ; return to shader part epilog
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172 main_body:
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173 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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174 ret <4 x float> %v
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175 }
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176
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177 define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
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178 ; GFX10-LABEL: sample_c_d_cl_2d:
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179 ; GFX10: ; %bb.0: ; %main_body
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180 ; GFX10-NEXT: v_and_b32_e32 v5, 0xffff, v5
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181 ; GFX10-NEXT: v_lshl_or_b32 v5, v6, 16, v5
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182 ; GFX10-NEXT: image_sample_c_d_cl v[0:3], [v0, v1, v2, v3, v4, v5, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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183 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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184 ; GFX10-NEXT: ; return to shader part epilog
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185 ;
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186 ; GFX10GISEL-LABEL: sample_c_d_cl_2d:
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187 ; GFX10GISEL: ; %bb.0: ; %main_body
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188 ; GFX10GISEL-NEXT: v_mov_b32_e32 v8, 0xffff
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189 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
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190 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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191 ; GFX10GISEL-NEXT: v_and_or_b32 v5, v5, v8, v6
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192 ; GFX10GISEL-NEXT: v_and_or_b32 v6, v7, v8, s12
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193 ; GFX10GISEL-NEXT: image_sample_c_d_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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194 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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195 ; GFX10GISEL-NEXT: ; return to shader part epilog
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196 main_body:
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197 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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198 ret <4 x float> %v
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199 }
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200
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201 define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s) {
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202 ; GFX10-LABEL: sample_cd_1d:
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203 ; GFX10: ; %bb.0: ; %main_body
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204 ; GFX10-NEXT: image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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205 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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206 ; GFX10-NEXT: ; return to shader part epilog
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207 ;
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208 ; GFX10GISEL-LABEL: sample_cd_1d:
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209 ; GFX10GISEL: ; %bb.0: ; %main_body
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210 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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211 ; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, s12
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212 ; GFX10GISEL-NEXT: image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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213 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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214 ; GFX10GISEL-NEXT: ; return to shader part epilog
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215 main_body:
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216 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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217 ret <4 x float> %v
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218 }
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219
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220 define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) {
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221 ; GFX10-LABEL: sample_cd_2d:
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222 ; GFX10: ; %bb.0: ; %main_body
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223 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v4
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224 ; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4
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225 ; GFX10-NEXT: image_sample_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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226 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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227 ; GFX10-NEXT: ; return to shader part epilog
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228 ;
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229 ; GFX10GISEL-LABEL: sample_cd_2d:
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230 ; GFX10GISEL: ; %bb.0: ; %main_body
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231 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
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232 ; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v4, v5
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233 ; GFX10GISEL-NEXT: image_sample_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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234 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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235 ; GFX10GISEL-NEXT: ; return to shader part epilog
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236 main_body:
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237 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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238 ret <4 x float> %v
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239 }
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240
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241 define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s) {
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242 ; GFX10-LABEL: sample_c_cd_1d:
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243 ; GFX10: ; %bb.0: ; %main_body
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244 ; GFX10-NEXT: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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245 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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246 ; GFX10-NEXT: ; return to shader part epilog
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247 ;
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248 ; GFX10GISEL-LABEL: sample_c_cd_1d:
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249 ; GFX10GISEL: ; %bb.0: ; %main_body
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250 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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251 ; GFX10GISEL-NEXT: v_and_or_b32 v3, 0xffff, v3, s12
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252 ; GFX10GISEL-NEXT: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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253 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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254 ; GFX10GISEL-NEXT: ; return to shader part epilog
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255 main_body:
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256 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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257 ret <4 x float> %v
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258 }
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259
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260 define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) {
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261 ; GFX10-LABEL: sample_c_cd_2d:
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262 ; GFX10: ; %bb.0: ; %main_body
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263 ; GFX10-NEXT: v_and_b32_e32 v5, 0xffff, v5
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264 ; GFX10-NEXT: v_lshl_or_b32 v5, v6, 16, v5
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265 ; GFX10-NEXT: image_sample_c_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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266 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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267 ; GFX10-NEXT: ; return to shader part epilog
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268 ;
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269 ; GFX10GISEL-LABEL: sample_c_cd_2d:
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270 ; GFX10GISEL: ; %bb.0: ; %main_body
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271 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
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272 ; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v5, v6
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273 ; GFX10GISEL-NEXT: image_sample_c_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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274 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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275 ; GFX10GISEL-NEXT: ; return to shader part epilog
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276 main_body:
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277 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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278 ret <4 x float> %v
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279 }
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280
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281 define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s, half %clamp) {
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282 ; GFX10-LABEL: sample_cd_cl_1d:
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283 ; GFX10: ; %bb.0: ; %main_body
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284 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2
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285 ; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2
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286 ; GFX10-NEXT: image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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287 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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288 ; GFX10-NEXT: ; return to shader part epilog
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289 ;
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290 ; GFX10GISEL-LABEL: sample_cd_cl_1d:
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291 ; GFX10GISEL: ; %bb.0: ; %main_body
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292 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
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293 ; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, v3
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294 ; GFX10GISEL-NEXT: image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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295 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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296 ; GFX10GISEL-NEXT: ; return to shader part epilog
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297 main_body:
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298 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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299 ret <4 x float> %v
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300 }
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301
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302 define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
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303 ; GFX10-LABEL: sample_cd_cl_2d:
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304 ; GFX10: ; %bb.0: ; %main_body
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305 ; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v4
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306 ; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4
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307 ; GFX10-NEXT: image_sample_cd_cl v[0:3], [v0, v1, v2, v3, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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308 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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309 ; GFX10-NEXT: ; return to shader part epilog
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310 ;
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311 ; GFX10GISEL-LABEL: sample_cd_cl_2d:
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312 ; GFX10GISEL: ; %bb.0: ; %main_body
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313 ; GFX10GISEL-NEXT: v_mov_b32_e32 v7, 0xffff
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314 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
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315 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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316 ; GFX10GISEL-NEXT: v_and_or_b32 v4, v4, v7, v5
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317 ; GFX10GISEL-NEXT: v_and_or_b32 v5, v6, v7, s12
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318 ; GFX10GISEL-NEXT: image_sample_cd_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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319 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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|
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320 ; GFX10GISEL-NEXT: ; return to shader part epilog
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|
321 main_body:
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|
322 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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|
|
323 ret <4 x float> %v
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|
|
324 }
|
|
|
325
|
|
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326 define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp) {
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327 ; GFX10-LABEL: sample_c_cd_cl_1d:
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|
|
328 ; GFX10: ; %bb.0: ; %main_body
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329 ; GFX10-NEXT: v_and_b32_e32 v3, 0xffff, v3
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330 ; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3
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|
|
331 ; GFX10-NEXT: image_sample_c_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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|
332 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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|
|
333 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
334 ;
|
|
|
335 ; GFX10GISEL-LABEL: sample_c_cd_cl_1d:
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|
|
336 ; GFX10GISEL: ; %bb.0: ; %main_body
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|
337 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4
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|
338 ; GFX10GISEL-NEXT: v_and_or_b32 v3, 0xffff, v3, v4
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|
|
339 ; GFX10GISEL-NEXT: image_sample_c_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
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|
|
340 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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|
|
341 ; GFX10GISEL-NEXT: ; return to shader part epilog
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|
342 main_body:
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|
|
343 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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|
|
344 ret <4 x float> %v
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|
|
345 }
|
|
|
346
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|
|
347 define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
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|
348 ; GFX10-LABEL: sample_c_cd_cl_2d:
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|
349 ; GFX10: ; %bb.0: ; %main_body
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|
350 ; GFX10-NEXT: v_and_b32_e32 v5, 0xffff, v5
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|
351 ; GFX10-NEXT: v_lshl_or_b32 v5, v6, 16, v5
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|
|
352 ; GFX10-NEXT: image_sample_c_cd_cl v[0:3], [v0, v1, v2, v3, v4, v5, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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|
|
353 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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|
354 ; GFX10-NEXT: ; return to shader part epilog
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|
|
355 ;
|
|
|
356 ; GFX10GISEL-LABEL: sample_c_cd_cl_2d:
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|
|
357 ; GFX10GISEL: ; %bb.0: ; %main_body
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|
|
358 ; GFX10GISEL-NEXT: v_mov_b32_e32 v8, 0xffff
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|
|
359 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
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|
|
360 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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|
|
361 ; GFX10GISEL-NEXT: v_and_or_b32 v5, v5, v8, v6
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|
|
362 ; GFX10GISEL-NEXT: v_and_or_b32 v6, v7, v8, s12
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|
|
363 ; GFX10GISEL-NEXT: image_sample_c_cd_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
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|
|
364 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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|
|
365 ; GFX10GISEL-NEXT: ; return to shader part epilog
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|
366 main_body:
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|
|
367 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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|
|
368 ret <4 x float> %v
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|
|
369 }
|
|
|
370
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|
|
371 define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice) {
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|
372 ; GFX10-LABEL: sample_c_d_o_2darray_V1:
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|
373 ; GFX10: ; %bb.0: ; %main_body
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|
374 ; GFX10-NEXT: v_and_b32_e32 v6, 0xffff, v6
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|
375 ; GFX10-NEXT: v_lshl_or_b32 v6, v7, 16, v6
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|
|
376 ; GFX10-NEXT: image_sample_c_d_o v0, [v0, v1, v2, v3, v4, v5, v6, v8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
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|
377 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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|
|
378 ; GFX10-NEXT: ; return to shader part epilog
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|
|
379 ;
|
|
|
380 ; GFX10GISEL-LABEL: sample_c_d_o_2darray_V1:
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|
|
381 ; GFX10GISEL: ; %bb.0: ; %main_body
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|
|
382 ; GFX10GISEL-NEXT: v_mov_b32_e32 v9, 0xffff
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|
|
383 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
|
384 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
|
|
385 ; GFX10GISEL-NEXT: v_and_or_b32 v6, v6, v9, v7
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|
|
386 ; GFX10GISEL-NEXT: v_and_or_b32 v7, v8, v9, s12
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|
|
387 ; GFX10GISEL-NEXT: image_sample_c_d_o v0, v[0:7], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
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|
|
388 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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|
|
389 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
390 main_body:
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|
|
391 %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f16(i32 4, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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|
|
392 ret float %v
|
|
|
393 }
|
|
|
394
|
|
|
395 define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice) {
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|
|
396 ; GFX10-LABEL: sample_c_d_o_2darray_V2:
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|
|
397 ; GFX10: ; %bb.0: ; %main_body
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|
|
398 ; GFX10-NEXT: v_and_b32_e32 v6, 0xffff, v6
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|
|
399 ; GFX10-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
|
400 ; GFX10-NEXT: image_sample_c_d_o v[0:1], [v0, v1, v2, v3, v4, v5, v6, v8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
|
|
|
401 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
402 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
403 ;
|
|
|
404 ; GFX10GISEL-LABEL: sample_c_d_o_2darray_V2:
|
|
|
405 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
406 ; GFX10GISEL-NEXT: v_mov_b32_e32 v9, 0xffff
|
|
|
407 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
|
408 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
|
|
409 ; GFX10GISEL-NEXT: v_and_or_b32 v6, v6, v9, v7
|
|
|
410 ; GFX10GISEL-NEXT: v_and_or_b32 v7, v8, v9, s12
|
|
|
411 ; GFX10GISEL-NEXT: image_sample_c_d_o v[0:1], v[0:7], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
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|
|
412 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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|
|
413 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
414 main_body:
|
|
|
415 %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f16(i32 6, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
416 ret <2 x float> %v
|
|
|
417 }
|
|
|
418
|
|
|
419 declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f16(i32, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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|
|
420 declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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|
|
421 declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32.f16(i32, float, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
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422 declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f16(i32, float, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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423 declare <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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424 declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f16(i32, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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425 declare <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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426 declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f16(i32, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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427 declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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428
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429 declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f16(i32, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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430 declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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431 declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f16(i32, float, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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432 declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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433 declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f16(i32, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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434 declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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435 declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f16(i32, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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436 declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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437
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438 declare float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f16(i32, i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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439 declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f16(i32, i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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440
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441 define amdgpu_ps <4 x float> @sample_g16_noa16_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
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442 ; GFX10-LABEL: sample_g16_noa16_d_1d:
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443 ; GFX10: ; %bb.0: ; %main_body
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444 ; GFX10-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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445 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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446 ; GFX10-NEXT: ; return to shader part epilog
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447 ;
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448 ; GFX10GISEL-LABEL: sample_g16_noa16_d_1d:
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449 ; GFX10GISEL: ; %bb.0: ; %main_body
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450 ; GFX10GISEL-NEXT: v_mov_b32_e32 v3, 0xffff
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451 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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452 ; GFX10GISEL-NEXT: v_and_or_b32 v0, v0, v3, s12
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453 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v3, s12
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454 ; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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455 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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456 ; GFX10GISEL-NEXT: ; return to shader part epilog
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457 main_body:
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458 %v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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459 ret <4 x float> %v
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460 }
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461
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462 define amdgpu_ps <4 x float> @sample_g16_noa16_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
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463 ; GFX10-LABEL: sample_g16_noa16_d_2d:
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464 ; GFX10: ; %bb.0: ; %main_body
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465 ; GFX10-NEXT: v_mov_b32_e32 v6, 0xffff
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466 ; GFX10-NEXT: v_and_b32_e32 v2, v6, v2
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467 ; GFX10-NEXT: v_and_b32_e32 v0, v6, v0
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468 ; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2
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469 ; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
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470 ; GFX10-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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471 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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472 ; GFX10-NEXT: ; return to shader part epilog
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473 ;
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474 ; GFX10GISEL-LABEL: sample_g16_noa16_d_2d:
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475 ; GFX10GISEL: ; %bb.0: ; %main_body
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476 ; GFX10GISEL-NEXT: v_mov_b32_e32 v6, 0xffff
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477 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
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478 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
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479 ; GFX10GISEL-NEXT: v_and_or_b32 v0, v0, v6, v1
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480 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v2, v6, v3
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481 ; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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482 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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483 ; GFX10GISEL-NEXT: ; return to shader part epilog
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484 main_body:
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485 %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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486 ret <4 x float> %v
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487 }
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488
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489 define amdgpu_ps <4 x float> @sample_g16_noa16_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r) {
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490 ; GFX10-LABEL: sample_g16_noa16_d_3d:
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491 ; GFX10: ; %bb.0: ; %main_body
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492 ; GFX10-NEXT: v_mov_b32_e32 v9, 0xffff
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493 ; GFX10-NEXT: v_and_b32_e32 v3, v9, v3
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494 ; GFX10-NEXT: v_and_b32_e32 v0, v9, v0
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495 ; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3
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496 ; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
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497 ; GFX10-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v6, v7, v8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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498 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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499 ; GFX10-NEXT: ; return to shader part epilog
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500 ;
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501 ; GFX10GISEL-LABEL: sample_g16_noa16_d_3d:
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502 ; GFX10GISEL: ; %bb.0: ; %main_body
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503 ; GFX10GISEL-NEXT: v_mov_b32_e32 v9, 0xffff
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504 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
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505 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4
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506 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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507 ; GFX10GISEL-NEXT: v_and_or_b32 v0, v0, v9, v1
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508 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v2, v9, s12
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509 ; GFX10GISEL-NEXT: v_and_or_b32 v2, v3, v9, v4
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510 ; GFX10GISEL-NEXT: v_and_or_b32 v3, v5, v9, s12
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511 ; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2, v3, v6, v7, v8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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512 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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513 ; GFX10GISEL-NEXT: ; return to shader part epilog
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514 main_body:
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515 %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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516 ret <4 x float> %v
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517 }
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518
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519 define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {
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520 ; GFX10-LABEL: sample_g16_noa16_c_d_1d:
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521 ; GFX10: ; %bb.0: ; %main_body
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522 ; GFX10-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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523 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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524 ; GFX10-NEXT: ; return to shader part epilog
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525 ;
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526 ; GFX10GISEL-LABEL: sample_g16_noa16_c_d_1d:
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527 ; GFX10GISEL: ; %bb.0: ; %main_body
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528 ; GFX10GISEL-NEXT: v_mov_b32_e32 v4, 0xffff
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529 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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530 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v4, s12
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531 ; GFX10GISEL-NEXT: v_and_or_b32 v2, v2, v4, s12
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532 ; GFX10GISEL-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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533 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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534 ; GFX10GISEL-NEXT: ; return to shader part epilog
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535 main_body:
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536 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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537 ret <4 x float> %v
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538 }
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539
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540 define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
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541 ; GFX10-LABEL: sample_g16_noa16_c_d_2d:
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542 ; GFX10: ; %bb.0: ; %main_body
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543 ; GFX10-NEXT: v_mov_b32_e32 v7, 0xffff
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544 ; GFX10-NEXT: v_and_b32_e32 v3, v7, v3
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545 ; GFX10-NEXT: v_and_b32_e32 v1, v7, v1
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546 ; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3
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547 ; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1
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548 ; GFX10-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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549 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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550 ; GFX10-NEXT: ; return to shader part epilog
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551 ;
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552 ; GFX10GISEL-LABEL: sample_g16_noa16_c_d_2d:
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553 ; GFX10GISEL: ; %bb.0: ; %main_body
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554 ; GFX10GISEL-NEXT: v_mov_b32_e32 v7, 0xffff
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555 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
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556 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4
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557 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v7, v2
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558 ; GFX10GISEL-NEXT: v_and_or_b32 v2, v3, v7, v4
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559 ; GFX10GISEL-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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560 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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561 ; GFX10GISEL-NEXT: ; return to shader part epilog
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562 main_body:
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563 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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564 ret <4 x float> %v
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565 }
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566
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567 define amdgpu_ps <4 x float> @sample_g16_noa16_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {
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568 ; GFX10-LABEL: sample_g16_noa16_d_cl_1d:
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569 ; GFX10: ; %bb.0: ; %main_body
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570 ; GFX10-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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571 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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572 ; GFX10-NEXT: ; return to shader part epilog
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573 ;
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574 ; GFX10GISEL-LABEL: sample_g16_noa16_d_cl_1d:
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575 ; GFX10GISEL: ; %bb.0: ; %main_body
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576 ; GFX10GISEL-NEXT: v_mov_b32_e32 v4, 0xffff
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577 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
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578 ; GFX10GISEL-NEXT: v_and_or_b32 v0, v0, v4, s12
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579 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v4, s12
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580 ; GFX10GISEL-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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581 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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582 ; GFX10GISEL-NEXT: ; return to shader part epilog
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583 main_body:
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584 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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585 ret <4 x float> %v
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586 }
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587
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588 define amdgpu_ps <4 x float> @sample_g16_noa16_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
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589 ; GFX10-LABEL: sample_g16_noa16_d_cl_2d:
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590 ; GFX10: ; %bb.0: ; %main_body
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591 ; GFX10-NEXT: v_mov_b32_e32 v7, 0xffff
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592 ; GFX10-NEXT: v_and_b32_e32 v2, v7, v2
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593 ; GFX10-NEXT: v_and_b32_e32 v0, v7, v0
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594 ; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2
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595 ; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
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596 ; GFX10-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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597 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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|
|
598 ; GFX10-NEXT: ; return to shader part epilog
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599 ;
|
|
|
600 ; GFX10GISEL-LABEL: sample_g16_noa16_d_cl_2d:
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601 ; GFX10GISEL: ; %bb.0: ; %main_body
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|
602 ; GFX10GISEL-NEXT: v_mov_b32_e32 v7, 0xffff
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603 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
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604 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
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|
605 ; GFX10GISEL-NEXT: v_and_or_b32 v0, v0, v7, v1
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|
606 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v2, v7, v3
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|
607 ; GFX10GISEL-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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|
|
608 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
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|
609 ; GFX10GISEL-NEXT: ; return to shader part epilog
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|
610 main_body:
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|
611 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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|
612 ret <4 x float> %v
|
|
|
613 }
|
|
|
614
|
|
|
615 define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
|
|
|
616 ; GFX10-LABEL: sample_g16_noa16_c_d_cl_1d:
|
|
|
617 ; GFX10: ; %bb.0: ; %main_body
|
|
|
618 ; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
|
619 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
620 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
621 ;
|
|
|
622 ; GFX10GISEL-LABEL: sample_g16_noa16_c_d_cl_1d:
|
|
|
623 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
624 ; GFX10GISEL-NEXT: v_mov_b32_e32 v5, 0xffff
|
|
|
625 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
|
|
626 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v5, s12
|
|
|
627 ; GFX10GISEL-NEXT: v_and_or_b32 v2, v2, v5, s12
|
|
|
628 ; GFX10GISEL-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
|
629 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
|
630 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
631 main_body:
|
|
|
632 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
633 ret <4 x float> %v
|
|
|
634 }
|
|
|
635
|
|
|
636 define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
|
|
|
637 ; GFX10-LABEL: sample_g16_noa16_c_d_cl_2d:
|
|
|
638 ; GFX10: ; %bb.0: ; %main_body
|
|
|
639 ; GFX10-NEXT: v_mov_b32_e32 v8, 0xffff
|
|
|
640 ; GFX10-NEXT: v_and_b32_e32 v3, v8, v3
|
|
|
641 ; GFX10-NEXT: v_and_b32_e32 v1, v8, v1
|
|
|
642 ; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
|
643 ; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
|
644 ; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
|
645 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
646 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
647 ;
|
|
|
648 ; GFX10GISEL-LABEL: sample_g16_noa16_c_d_cl_2d:
|
|
|
649 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
650 ; GFX10GISEL-NEXT: v_mov_b32_e32 v8, 0xffff
|
|
|
651 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
|
652 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
|
653 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v8, v2
|
|
|
654 ; GFX10GISEL-NEXT: v_and_or_b32 v2, v3, v8, v4
|
|
|
655 ; GFX10GISEL-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
|
656 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
|
657 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
658 main_body:
|
|
|
659 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
660 ret <4 x float> %v
|
|
|
661 }
|
|
|
662
|
|
|
663 define amdgpu_ps <4 x float> @sample_g16_noa16_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
|
|
|
664 ; GFX10-LABEL: sample_g16_noa16_cd_1d:
|
|
|
665 ; GFX10: ; %bb.0: ; %main_body
|
|
|
666 ; GFX10-NEXT: image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
|
667 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
668 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
669 ;
|
|
|
670 ; GFX10GISEL-LABEL: sample_g16_noa16_cd_1d:
|
|
|
671 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
672 ; GFX10GISEL-NEXT: v_mov_b32_e32 v3, 0xffff
|
|
|
673 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
|
|
674 ; GFX10GISEL-NEXT: v_and_or_b32 v0, v0, v3, s12
|
|
|
675 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v3, s12
|
|
|
676 ; GFX10GISEL-NEXT: image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
|
677 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
|
678 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
679 main_body:
|
|
|
680 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
681 ret <4 x float> %v
|
|
|
682 }
|
|
|
683
|
|
|
684 define amdgpu_ps <4 x float> @sample_g16_noa16_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
|
|
|
685 ; GFX10-LABEL: sample_g16_noa16_cd_2d:
|
|
|
686 ; GFX10: ; %bb.0: ; %main_body
|
|
|
687 ; GFX10-NEXT: v_mov_b32_e32 v6, 0xffff
|
|
|
688 ; GFX10-NEXT: v_and_b32_e32 v2, v6, v2
|
|
|
689 ; GFX10-NEXT: v_and_b32_e32 v0, v6, v0
|
|
|
690 ; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
|
691 ; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
|
692 ; GFX10-NEXT: image_sample_cd_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
|
693 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
694 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
695 ;
|
|
|
696 ; GFX10GISEL-LABEL: sample_g16_noa16_cd_2d:
|
|
|
697 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
698 ; GFX10GISEL-NEXT: v_mov_b32_e32 v6, 0xffff
|
|
|
699 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
|
700 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
|
701 ; GFX10GISEL-NEXT: v_and_or_b32 v0, v0, v6, v1
|
|
|
702 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v2, v6, v3
|
|
|
703 ; GFX10GISEL-NEXT: image_sample_cd_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
|
704 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
|
705 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
706 main_body:
|
|
|
707 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
708 ret <4 x float> %v
|
|
|
709 }
|
|
|
710
|
|
|
711 define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {
|
|
|
712 ; GFX10-LABEL: sample_g16_noa16_c_cd_1d:
|
|
|
713 ; GFX10: ; %bb.0: ; %main_body
|
|
|
714 ; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
|
715 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
716 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
717 ;
|
|
|
718 ; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_1d:
|
|
|
719 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
720 ; GFX10GISEL-NEXT: v_mov_b32_e32 v4, 0xffff
|
|
|
721 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
|
|
722 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v4, s12
|
|
|
723 ; GFX10GISEL-NEXT: v_and_or_b32 v2, v2, v4, s12
|
|
|
724 ; GFX10GISEL-NEXT: image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
|
725 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
|
726 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
727 main_body:
|
|
|
728 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
729 ret <4 x float> %v
|
|
|
730 }
|
|
|
731
|
|
|
732 define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
|
|
|
733 ; GFX10-LABEL: sample_g16_noa16_c_cd_2d:
|
|
|
734 ; GFX10: ; %bb.0: ; %main_body
|
|
|
735 ; GFX10-NEXT: v_mov_b32_e32 v7, 0xffff
|
|
|
736 ; GFX10-NEXT: v_and_b32_e32 v3, v7, v3
|
|
|
737 ; GFX10-NEXT: v_and_b32_e32 v1, v7, v1
|
|
|
738 ; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
|
739 ; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
|
740 ; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
|
741 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
742 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
743 ;
|
|
|
744 ; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_2d:
|
|
|
745 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
746 ; GFX10GISEL-NEXT: v_mov_b32_e32 v7, 0xffff
|
|
|
747 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
|
748 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
|
749 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v7, v2
|
|
|
750 ; GFX10GISEL-NEXT: v_and_or_b32 v2, v3, v7, v4
|
|
|
751 ; GFX10GISEL-NEXT: image_sample_c_cd_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
|
752 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
|
753 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
754 main_body:
|
|
|
755 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
756 ret <4 x float> %v
|
|
|
757 }
|
|
|
758
|
|
|
759 define amdgpu_ps <4 x float> @sample_g16_noa16_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {
|
|
|
760 ; GFX10-LABEL: sample_g16_noa16_cd_cl_1d:
|
|
|
761 ; GFX10: ; %bb.0: ; %main_body
|
|
|
762 ; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
|
763 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
764 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
765 ;
|
|
|
766 ; GFX10GISEL-LABEL: sample_g16_noa16_cd_cl_1d:
|
|
|
767 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
768 ; GFX10GISEL-NEXT: v_mov_b32_e32 v4, 0xffff
|
|
|
769 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
|
|
770 ; GFX10GISEL-NEXT: v_and_or_b32 v0, v0, v4, s12
|
|
|
771 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v4, s12
|
|
|
772 ; GFX10GISEL-NEXT: image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
|
773 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
|
774 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
775 main_body:
|
|
|
776 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
777 ret <4 x float> %v
|
|
|
778 }
|
|
|
779
|
|
|
780 define amdgpu_ps <4 x float> @sample_g16_noa16_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
|
|
|
781 ; GFX10-LABEL: sample_g16_noa16_cd_cl_2d:
|
|
|
782 ; GFX10: ; %bb.0: ; %main_body
|
|
|
783 ; GFX10-NEXT: v_mov_b32_e32 v7, 0xffff
|
|
|
784 ; GFX10-NEXT: v_and_b32_e32 v2, v7, v2
|
|
|
785 ; GFX10-NEXT: v_and_b32_e32 v0, v7, v0
|
|
|
786 ; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
|
787 ; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
|
788 ; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
|
789 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
790 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
791 ;
|
|
|
792 ; GFX10GISEL-LABEL: sample_g16_noa16_cd_cl_2d:
|
|
|
793 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
794 ; GFX10GISEL-NEXT: v_mov_b32_e32 v7, 0xffff
|
|
|
795 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
|
796 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
|
797 ; GFX10GISEL-NEXT: v_and_or_b32 v0, v0, v7, v1
|
|
|
798 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v2, v7, v3
|
|
|
799 ; GFX10GISEL-NEXT: image_sample_cd_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
|
800 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
|
801 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
802 main_body:
|
|
|
803 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
804 ret <4 x float> %v
|
|
|
805 }
|
|
|
806
|
|
|
807 define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
|
|
|
808 ; GFX10-LABEL: sample_g16_noa16_c_cd_cl_1d:
|
|
|
809 ; GFX10: ; %bb.0: ; %main_body
|
|
|
810 ; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
|
811 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
812 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
813 ;
|
|
|
814 ; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_cl_1d:
|
|
|
815 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
816 ; GFX10GISEL-NEXT: v_mov_b32_e32 v5, 0xffff
|
|
|
817 ; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
|
|
818 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v5, s12
|
|
|
819 ; GFX10GISEL-NEXT: v_and_or_b32 v2, v2, v5, s12
|
|
|
820 ; GFX10GISEL-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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|
821 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
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|
822 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
823 main_body:
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|
|
824 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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|
825 ret <4 x float> %v
|
|
|
826 }
|
|
|
827
|
|
|
828 define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
|
|
|
829 ; GFX10-LABEL: sample_g16_noa16_c_cd_cl_2d:
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|
830 ; GFX10: ; %bb.0: ; %main_body
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|
831 ; GFX10-NEXT: v_mov_b32_e32 v8, 0xffff
|
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|
832 ; GFX10-NEXT: v_and_b32_e32 v3, v8, v3
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|
833 ; GFX10-NEXT: v_and_b32_e32 v1, v8, v1
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|
|
834 ; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
|
835 ; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
|
836 ; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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|
|
837 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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|
|
838 ; GFX10-NEXT: ; return to shader part epilog
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|
|
839 ;
|
|
|
840 ; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_cl_2d:
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|
841 ; GFX10GISEL: ; %bb.0: ; %main_body
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|
842 ; GFX10GISEL-NEXT: v_mov_b32_e32 v8, 0xffff
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|
843 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
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|
|
844 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
|
845 ; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v8, v2
|
|
|
846 ; GFX10GISEL-NEXT: v_and_or_b32 v2, v3, v8, v4
|
|
|
847 ; GFX10GISEL-NEXT: image_sample_c_cd_cl_g16 v[0:3], [v0, v1, v2, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
|
848 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
|
849 ; GFX10GISEL-NEXT: ; return to shader part epilog
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|
850 main_body:
|
|
|
851 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
852 ret <4 x float> %v
|
|
|
853 }
|
|
|
854
|
|
|
855 define amdgpu_ps float @sample_g16_noa16_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {
|
|
|
856 ; GFX10-LABEL: sample_g16_noa16_c_d_o_2darray_V1:
|
|
|
857 ; GFX10: ; %bb.0: ; %main_body
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|
|
858 ; GFX10-NEXT: v_mov_b32_e32 v9, 0xffff
|
|
|
859 ; GFX10-NEXT: v_and_b32_e32 v4, v9, v4
|
|
|
860 ; GFX10-NEXT: v_and_b32_e32 v2, v9, v2
|
|
|
861 ; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
|
862 ; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
|
863 ; GFX10-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v6, v7, v8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
|
|
|
864 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
865 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
866 ;
|
|
|
867 ; GFX10GISEL-LABEL: sample_g16_noa16_c_d_o_2darray_V1:
|
|
|
868 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
869 ; GFX10GISEL-NEXT: v_mov_b32_e32 v9, 0xffff
|
|
|
870 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
|
871 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
|
872 ; GFX10GISEL-NEXT: v_and_or_b32 v2, v2, v9, v3
|
|
|
873 ; GFX10GISEL-NEXT: v_and_or_b32 v3, v4, v9, v5
|
|
|
874 ; GFX10GISEL-NEXT: image_sample_c_d_o_g16 v0, [v0, v1, v2, v3, v6, v7, v8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
|
|
|
875 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
|
876 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
877 main_body:
|
|
|
878 %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
879 ret float %v
|
|
|
880 }
|
|
|
881
|
|
|
882 define amdgpu_ps <2 x float> @sample_g16_noa16_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {
|
|
|
883 ; GFX10-LABEL: sample_g16_noa16_c_d_o_2darray_V2:
|
|
|
884 ; GFX10: ; %bb.0: ; %main_body
|
|
|
885 ; GFX10-NEXT: v_mov_b32_e32 v9, 0xffff
|
|
|
886 ; GFX10-NEXT: v_and_b32_e32 v4, v9, v4
|
|
|
887 ; GFX10-NEXT: v_and_b32_e32 v2, v9, v2
|
|
|
888 ; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
|
889 ; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
|
890 ; GFX10-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v6, v7, v8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
|
|
|
891 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
892 ; GFX10-NEXT: ; return to shader part epilog
|
|
|
893 ;
|
|
|
894 ; GFX10GISEL-LABEL: sample_g16_noa16_c_d_o_2darray_V2:
|
|
|
895 ; GFX10GISEL: ; %bb.0: ; %main_body
|
|
|
896 ; GFX10GISEL-NEXT: v_mov_b32_e32 v9, 0xffff
|
|
|
897 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
|
898 ; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
|
899 ; GFX10GISEL-NEXT: v_and_or_b32 v2, v2, v9, v3
|
|
|
900 ; GFX10GISEL-NEXT: v_and_or_b32 v3, v4, v9, v5
|
|
|
901 ; GFX10GISEL-NEXT: image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v3, v6, v7, v8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
|
|
|
902 ; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
|
903 ; GFX10GISEL-NEXT: ; return to shader part epilog
|
|
|
904 main_body:
|
|
|
905 %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
|
906 ret <2 x float> %v
|
|
|
907 }
|
|
|
908
|
|
|
909 declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
910 declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
911 declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32, half, half, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
912 declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
913 declare <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
914 declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
915 declare <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
916 declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
917 declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
918
|
|
|
919 declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
920 declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
921 declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
922 declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
923 declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
924 declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
925 declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
926 declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
927
|
|
|
928 declare float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
929 declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
|
930
|
|
|
931 attributes #0 = { nounwind }
|
|
|
932 attributes #1 = { nounwind readonly }
|
|
|
933 attributes #2 = { nounwind readnone }
|
