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1 //===-- MicroMipsDSPInstrFormats.td - Instruction Formats --*- tablegen -*-===//
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2 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 // The LLVM Compiler Infrastructure
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4 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 class MMDSPInst<string opstr = "">
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11 : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
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12 let InsnPredicates = [HasDSP];
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100
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13 let AdditionalPredicates = [InMicroMips];
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14 string BaseOpcode = opstr;
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15 string Arch = "mmdsp";
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16 let DecoderNamespace = "MicroMips";
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17 }
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18
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100
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19 class MMDSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
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20 : InstAlias<Asm, Result, Emit>, PredicateControl {
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21 let InsnPredicates = [HasDSP];
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22 let AdditionalPredicates = [InMicroMips];
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23 }
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24
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25 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
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26 bits<5> rd;
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27 bits<5> rs;
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28 bits<5> rt;
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29
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30 let Inst{31-26} = 0b000000;
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31 let Inst{25-21} = rt;
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32 let Inst{20-16} = rs;
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33 let Inst{15-11} = rd;
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34 let Inst{10-0} = op;
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35 }
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36
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37 class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
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38 bits<5> rt;
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39 bits<5> rs;
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40
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41 let Inst{31-26} = 0b000000;
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42 let Inst{25-21} = rt;
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43 let Inst{20-16} = rs;
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44 let Inst{15-6} = op;
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45 let Inst{5-0} = 0b111100;
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46 }
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47
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48 class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
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49 bits<5> rt;
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50 bits<5> rs;
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51 bits<2> ac;
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52
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53 let Inst{31-26} = 0b000000;
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54 let Inst{25-21} = rt;
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55 let Inst{20-16} = rs;
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56 let Inst{15-14} = ac;
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57 let Inst{13-6} = op;
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58 let Inst{5-0} = 0b111100;
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59 }
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60
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61 class POOL32A_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
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62 bits<5> rd;
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63 bits<5> rs;
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64 bits<5> rt;
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65
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66 let Inst{31-26} = 0b000000;
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67 let Inst{25-21} = rt;
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68 let Inst{20-16} = rs;
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69 let Inst{15-11} = rd;
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70 let Inst{10} = 0b0;
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71 let Inst{9-0} = op;
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72 }
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73
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74 class POOL32A_2RSA4_FMT<string opstr, bits<12> op> : MMDSPInst<opstr> {
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75 bits<5> rt;
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76 bits<5> rs;
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77 bits<4> sa;
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78
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79 let Inst{31-26} = 0b000000;
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80 let Inst{25-21} = rt;
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81 let Inst{20-16} = rs;
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82 let Inst{15-12} = sa;
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83 let Inst{11-0} = op;
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84 }
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85
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86 class POOL32A_2RSA3_FMT<string opstr, bits<7> op> : MMDSPInst<opstr> {
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87 bits<5> rt;
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88 bits<5> rs;
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89 bits<3> sa;
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90
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91 let Inst{31-26} = 0b000000;
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92 let Inst{25-21} = rt;
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93 let Inst{20-16} = rs;
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94 let Inst{15-13} = sa;
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95 let Inst{12-6} = op;
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96 let Inst{5-0} = 0b111100;
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97 }
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98
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99 class POOL32A_2RSA5B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
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100 bits<5> rt;
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101 bits<5> rs;
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102 bits<5> sa;
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103
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104 let Inst{31-26} = 0b000000;
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105 let Inst{25-21} = rt;
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106 let Inst{20-16} = rs;
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107 let Inst{15-11} = sa;
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108 let Inst{10} = 0b0;
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109 let Inst{9-0} = op;
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110 }
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111
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112 class POOL32A_2RSA4B0_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
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113 bits<5> rt;
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114 bits<5> rs;
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115 bits<4> sa;
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116
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117 let Inst{31-26} = 0b000000;
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118 let Inst{25-21} = rt;
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119 let Inst{20-16} = rs;
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120 let Inst{15-12} = sa;
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121 let Inst{11} = 0b0;
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122 let Inst{10-0} = op;
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123 }
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124
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125 class POOL32A_2RSA4OP6_FMT<string opstr, bits<6> op> : MMDSPInst<opstr> {
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126 bits<5> rt;
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127 bits<5> rs;
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128 bits<4> sa;
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129
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130 let Inst{31-26} = 0b000000;
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131 let Inst{25-21} = rt;
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132 let Inst{20-16} = rs;
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133 let Inst{15-12} = sa;
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134 let Inst{11-6} = op;
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135 let Inst{5-0} = 0b111100;
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136 }
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137
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138 class POOL32A_1RIMM5AC_FMT<string opstr, bits<8> funct> : MMDSPInst<opstr> {
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139 bits<5> rt;
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140 bits<5> imm;
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141 bits<2> ac;
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142
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143 let Inst{31-26} = 0b000000;
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144 let Inst{25-21} = rt;
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145 let Inst{20-16} = imm;
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146 let Inst{15-14} = ac;
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147 let Inst{13-6} = funct;
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148 let Inst{5-0} = 0b111100;
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149 }
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150
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151 class POOL32A_2RSA5_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
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152 bits<5> rt;
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153 bits<5> rs;
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154 bits<5> sa;
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155
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156 let Inst{31-26} = 0b000000;
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157 let Inst{25-21} = rt;
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158 let Inst{20-16} = rs;
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159 let Inst{15-11} = sa;
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160 let Inst{10-0} = op;
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161 }
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162
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163 class POOL32A_1RMEMB0_FMT<string opstr, bits<10> funct> : MMDSPInst<opstr> {
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164 bits<5> index;
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165 bits<5> base;
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166 bits<5> rd;
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167
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168 let Inst{31-26} = 0;
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169 let Inst{25-21} = index;
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170 let Inst{20-16} = base;
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171 let Inst{15-11} = rd;
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172 let Inst{10} = 0b0;
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173 let Inst{9-0} = funct;
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174 }
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175
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176 class POOL32A_1RAC_FMT<string instr_asm, bits<8> funct> : MMDSPInst<instr_asm> {
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177 bits<5> rs;
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178 bits<2> ac;
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179
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180 let Inst{31-26} = 0;
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181 let Inst{25-21} = 0;
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182 let Inst{20-16} = rs;
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183 let Inst{15-14} = ac;
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184 let Inst{13-6} = funct;
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185 let Inst{5-0} = 0b111100;
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186 }
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187
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188 class POOL32A_1RMASK7_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
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189 bits<5> rt;
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190 bits<7> mask;
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191
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192 let Inst{31-26} = 0b000000;
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193 let Inst{25-21} = rt;
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194 let Inst{20-14} = mask;
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195 let Inst{13-6} = op;
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196 let Inst{5-0} = 0b111100;
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197 }
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198
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199 class POOL32A_1RIMM10_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
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200 bits<5> rd;
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201 bits<10> imm;
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202
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203 let Inst{31-26} = 0;
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204 let Inst{25-16} = imm;
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205 let Inst{15-11} = rd;
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206 let Inst{10} = 0;
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207 let Inst{9-0} = op;
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208 }
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209
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210 class POOL32A_1RIMM8_FMT<string opstr, bits<6> op> : MMDSPInst<opstr> {
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211 bits<5> rt;
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212 bits<8> imm;
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213
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214 let Inst{31-26} = 0;
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215 let Inst{25-21} = rt;
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216 let Inst{20-13} = imm;
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217 let Inst{12} = 0;
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218 let Inst{11-6} = op;
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219 let Inst{5-0} = 0b111100;
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220 }
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221
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222 class POOL32A_4B0SHIFT6AC4B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
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223 bits<6> shift;
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224 bits<2> ac;
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225
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226 let Inst{31-26} = 0b000000;
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227 let Inst{25-22} = 0b0000;
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228 let Inst{21-16} = shift;
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229 let Inst{15-14} = ac;
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230 let Inst{13-10} = 0b0000;
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231 let Inst{9-0} = op;
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232 }
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233
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234 class POOL32A_5B01RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
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235 bits<5> rs;
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236 bits<2> ac;
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237
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238 let Inst{31-26} = 0b000000;
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239 let Inst{25-21} = 0b00000;
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240 let Inst{20-16} = rs;
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241 let Inst{15-14} = ac;
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242 let Inst{13-6} = op;
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243 let Inst{5-0} = 0b111100;
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244 }
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