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1 //===--------------- PPCVSXFMAMutate.cpp - VSX FMA Mutation ---------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This pass mutates the form of VSX FMA instructions to avoid unnecessary
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11 // copies.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 #include "PPCInstrInfo.h"
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16 #include "MCTargetDesc/PPCPredicates.h"
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17 #include "PPC.h"
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18 #include "PPCInstrBuilder.h"
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19 #include "PPCMachineFunctionInfo.h"
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20 #include "PPCTargetMachine.h"
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21 #include "llvm/ADT/STLExtras.h"
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22 #include "llvm/ADT/Statistic.h"
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23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
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24 #include "llvm/CodeGen/MachineFrameInfo.h"
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25 #include "llvm/CodeGen/MachineFunctionPass.h"
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26 #include "llvm/CodeGen/MachineInstrBuilder.h"
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27 #include "llvm/CodeGen/MachineMemOperand.h"
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28 #include "llvm/CodeGen/MachineRegisterInfo.h"
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29 #include "llvm/CodeGen/PseudoSourceValue.h"
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30 #include "llvm/CodeGen/ScheduleDAG.h"
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31 #include "llvm/CodeGen/SlotIndexes.h"
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32 #include "llvm/MC/MCAsmInfo.h"
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33 #include "llvm/Support/CommandLine.h"
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34 #include "llvm/Support/Debug.h"
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35 #include "llvm/Support/ErrorHandling.h"
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36 #include "llvm/Support/TargetRegistry.h"
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37 #include "llvm/Support/raw_ostream.h"
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38
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39 using namespace llvm;
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40
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41 static cl::opt<bool> DisableVSXFMAMutate("disable-ppc-vsx-fma-mutation",
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42 cl::desc("Disable VSX FMA instruction mutation"), cl::Hidden);
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43
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44 #define DEBUG_TYPE "ppc-vsx-fma-mutate"
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45
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46 namespace llvm { namespace PPC {
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47 int getAltVSXFMAOpcode(uint16_t Opcode);
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48 } }
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49
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50 namespace {
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51 // PPCVSXFMAMutate pass - For copies between VSX registers and non-VSX registers
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52 // (Altivec and scalar floating-point registers), we need to transform the
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53 // copies into subregister copies with other restrictions.
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54 struct PPCVSXFMAMutate : public MachineFunctionPass {
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55 static char ID;
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56 PPCVSXFMAMutate() : MachineFunctionPass(ID) {
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57 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
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58 }
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59
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60 LiveIntervals *LIS;
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61 const PPCInstrInfo *TII;
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62
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63 protected:
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64 bool processBlock(MachineBasicBlock &MBB) {
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65 bool Changed = false;
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66
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67 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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68 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
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69 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
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70 I != IE; ++I) {
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71 MachineInstr *MI = I;
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72
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73 // The default (A-type) VSX FMA form kills the addend (it is taken from
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74 // the target register, which is then updated to reflect the result of
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75 // the FMA). If the instruction, however, kills one of the registers
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76 // used for the product, then we can use the M-form instruction (which
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77 // will take that value from the to-be-defined register).
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78
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79 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
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80 if (AltOpc == -1)
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81 continue;
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82
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83 // This pass is run after register coalescing, and so we're looking for
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84 // a situation like this:
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85 // ...
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86 // %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
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87 // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
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88 // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
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89 // ...
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90 // %vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19,
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91 // %RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19
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92 // ...
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93 // Where we can eliminate the copy by changing from the A-type to the
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94 // M-type instruction. Specifically, for this example, this means:
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95 // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
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96 // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
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97 // is replaced by:
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98 // %vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9,
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99 // %RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9
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100 // and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
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101
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102 SlotIndex FMAIdx = LIS->getInstructionIndex(MI);
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103
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104 VNInfo *AddendValNo =
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105 LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn();
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95
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106
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107 // This can be null if the register is undef.
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108 if (!AddendValNo)
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109 continue;
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110
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83
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111 MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def);
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112
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113 // The addend and this instruction must be in the same block.
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114
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115 if (!AddendMI || AddendMI->getParent() != MI->getParent())
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116 continue;
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117
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118 // The addend must be a full copy within the same register class.
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119
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120 if (!AddendMI->isFullCopy())
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121 continue;
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122
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123 unsigned AddendSrcReg = AddendMI->getOperand(1).getReg();
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124 if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg)) {
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125 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
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126 MRI.getRegClass(AddendSrcReg))
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127 continue;
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128 } else {
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129 // If AddendSrcReg is a physical register, make sure the destination
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130 // register class contains it.
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131 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
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132 ->contains(AddendSrcReg))
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133 continue;
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134 }
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135
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136 // In theory, there could be other uses of the addend copy before this
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137 // fma. We could deal with this, but that would require additional
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138 // logic below and I suspect it will not occur in any relevant
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139 // situations. Additionally, check whether the copy source is killed
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140 // prior to the fma. In order to replace the addend here with the
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141 // source of the copy, it must still be live here. We can't use
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142 // interval testing for a physical register, so as long as we're
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143 // walking the MIs we may as well test liveness here.
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95
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144 //
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145 // FIXME: There is a case that occurs in practice, like this:
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146 // %vreg9<def> = COPY %F1; VSSRC:%vreg9
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147 // ...
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148 // %vreg6<def> = COPY %vreg9; VSSRC:%vreg6,%vreg9
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149 // %vreg7<def> = COPY %vreg9; VSSRC:%vreg7,%vreg9
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150 // %vreg9<def,tied1> = XSMADDASP %vreg9<tied0>, %vreg1, %vreg4; VSSRC:
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151 // %vreg6<def,tied1> = XSMADDASP %vreg6<tied0>, %vreg1, %vreg2; VSSRC:
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152 // %vreg7<def,tied1> = XSMADDASP %vreg7<tied0>, %vreg1, %vreg3; VSSRC:
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153 // which prevents an otherwise-profitable transformation.
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83
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154 bool OtherUsers = false, KillsAddendSrc = false;
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155 for (auto J = std::prev(I), JE = MachineBasicBlock::iterator(AddendMI);
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156 J != JE; --J) {
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157 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) {
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158 OtherUsers = true;
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159 break;
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160 }
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161 if (J->modifiesRegister(AddendSrcReg, TRI) ||
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162 J->killsRegister(AddendSrcReg, TRI)) {
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163 KillsAddendSrc = true;
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164 break;
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165 }
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166 }
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167
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168 if (OtherUsers || KillsAddendSrc)
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169 continue;
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170
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171 // Find one of the product operands that is killed by this instruction.
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172
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173 unsigned KilledProdOp = 0, OtherProdOp = 0;
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174 if (LIS->getInterval(MI->getOperand(2).getReg())
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175 .Query(FMAIdx).isKill()) {
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176 KilledProdOp = 2;
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177 OtherProdOp = 3;
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178 } else if (LIS->getInterval(MI->getOperand(3).getReg())
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179 .Query(FMAIdx).isKill()) {
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180 KilledProdOp = 3;
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181 OtherProdOp = 2;
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182 }
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183
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184 // If there are no killed product operands, then this transformation is
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185 // likely not profitable.
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186 if (!KilledProdOp)
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187 continue;
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188
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95
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189 // If the addend copy is used only by this MI, then the addend source
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190 // register is likely not live here. This could be fixed (based on the
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191 // legality checks above, the live range for the addend source register
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192 // could be extended), but it seems likely that such a trivial copy can
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193 // be coalesced away later, and thus is not worth the effort.
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194 if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg) &&
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195 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx))
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196 continue;
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83
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197
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198 // Transform: (O2 * O3) + O1 -> (O2 * O1) + O3.
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199
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200 unsigned KilledProdReg = MI->getOperand(KilledProdOp).getReg();
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201 unsigned OtherProdReg = MI->getOperand(OtherProdOp).getReg();
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202
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203 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg();
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204 unsigned KilledProdSubReg = MI->getOperand(KilledProdOp).getSubReg();
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205 unsigned OtherProdSubReg = MI->getOperand(OtherProdOp).getSubReg();
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206
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207 bool AddRegKill = AddendMI->getOperand(1).isKill();
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208 bool KilledProdRegKill = MI->getOperand(KilledProdOp).isKill();
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209 bool OtherProdRegKill = MI->getOperand(OtherProdOp).isKill();
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210
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211 bool AddRegUndef = AddendMI->getOperand(1).isUndef();
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212 bool KilledProdRegUndef = MI->getOperand(KilledProdOp).isUndef();
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213 bool OtherProdRegUndef = MI->getOperand(OtherProdOp).isUndef();
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214
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215 unsigned OldFMAReg = MI->getOperand(0).getReg();
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216
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217 // The transformation doesn't work well with things like:
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218 // %vreg5 = A-form-op %vreg5, %vreg11, %vreg5;
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219 // so leave such things alone.
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220 if (OldFMAReg == KilledProdReg)
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221 continue;
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222
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100
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223 // If there isn't a class that fits, we can't perform the transform.
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224 // This is needed for correctness with a mixture of VSX and Altivec
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225 // instructions to make sure that a low VSX register is not assigned to
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226 // the Altivec instruction.
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227 if (!MRI.constrainRegClass(KilledProdReg,
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228 MRI.getRegClass(OldFMAReg)))
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229 continue;
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230
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83
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231 assert(OldFMAReg == AddendMI->getOperand(0).getReg() &&
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232 "Addend copy not tied to old FMA output!");
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233
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234 DEBUG(dbgs() << "VSX FMA Mutation:\n " << *MI;);
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235
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236 MI->getOperand(0).setReg(KilledProdReg);
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237 MI->getOperand(1).setReg(KilledProdReg);
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238 MI->getOperand(3).setReg(AddendSrcReg);
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83
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239 MI->getOperand(2).setReg(OtherProdReg);
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240
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241 MI->getOperand(0).setSubReg(KilledProdSubReg);
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242 MI->getOperand(1).setSubReg(KilledProdSubReg);
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243 MI->getOperand(3).setSubReg(AddSubReg);
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244 MI->getOperand(2).setSubReg(OtherProdSubReg);
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245
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246 MI->getOperand(1).setIsKill(KilledProdRegKill);
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247 MI->getOperand(3).setIsKill(AddRegKill);
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248 MI->getOperand(2).setIsKill(OtherProdRegKill);
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249
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250 MI->getOperand(1).setIsUndef(KilledProdRegUndef);
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251 MI->getOperand(3).setIsUndef(AddRegUndef);
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252 MI->getOperand(2).setIsUndef(OtherProdRegUndef);
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253
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254 MI->setDesc(TII->get(AltOpc));
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255
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256 DEBUG(dbgs() << " -> " << *MI);
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257
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258 // The killed product operand was killed here, so we can reuse it now
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259 // for the result of the fma.
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260
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261 LiveInterval &FMAInt = LIS->getInterval(OldFMAReg);
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262 VNInfo *FMAValNo = FMAInt.getVNInfoAt(FMAIdx.getRegSlot());
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263 for (auto UI = MRI.reg_nodbg_begin(OldFMAReg), UE = MRI.reg_nodbg_end();
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264 UI != UE;) {
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265 MachineOperand &UseMO = *UI;
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266 MachineInstr *UseMI = UseMO.getParent();
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267 ++UI;
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268
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269 // Don't replace the result register of the copy we're about to erase.
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270 if (UseMI == AddendMI)
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271 continue;
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272
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273 UseMO.substVirtReg(KilledProdReg, KilledProdSubReg, *TRI);
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83
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274 }
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275
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276 // Extend the live intervals of the killed product operand to hold the
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277 // fma result.
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278
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279 LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg);
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280 for (LiveInterval::iterator AI = FMAInt.begin(), AE = FMAInt.end();
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281 AI != AE; ++AI) {
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282 // Don't add the segment that corresponds to the original copy.
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283 if (AI->valno == AddendValNo)
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284 continue;
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285
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286 VNInfo *NewFMAValNo =
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287 NewFMAInt.getNextValue(AI->start,
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288 LIS->getVNInfoAllocator());
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289
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290 NewFMAInt.addSegment(LiveInterval::Segment(AI->start, AI->end,
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291 NewFMAValNo));
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292 }
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293 DEBUG(dbgs() << " extended: " << NewFMAInt << '\n');
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294
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95
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295 // Extend the live interval of the addend source (it might end at the
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296 // copy to be removed, or somewhere in between there and here). This
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297 // is necessary only if it is a physical register.
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298 if (!TargetRegisterInfo::isVirtualRegister(AddendSrcReg))
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299 for (MCRegUnitIterator Units(AddendSrcReg, TRI); Units.isValid();
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300 ++Units) {
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301 unsigned Unit = *Units;
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302
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303 LiveRange &AddendSrcRange = LIS->getRegUnit(Unit);
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304 AddendSrcRange.extendInBlock(LIS->getMBBStartIdx(&MBB),
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305 FMAIdx.getRegSlot());
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306 DEBUG(dbgs() << " extended: " << AddendSrcRange << '\n');
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307 }
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308
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83
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309 FMAInt.removeValNo(FMAValNo);
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310 DEBUG(dbgs() << " trimmed: " << FMAInt << '\n');
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311
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312 // Remove the (now unused) copy.
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313
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314 DEBUG(dbgs() << " removing: " << *AddendMI << '\n');
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315 LIS->RemoveMachineInstrFromMaps(AddendMI);
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316 AddendMI->eraseFromParent();
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317
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318 Changed = true;
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319 }
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320
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321 return Changed;
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322 }
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323
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324 public:
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325 bool runOnMachineFunction(MachineFunction &MF) override {
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326 // If we don't have VSX then go ahead and return without doing
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327 // anything.
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328 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
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329 if (!STI.hasVSX())
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330 return false;
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331
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332 LIS = &getAnalysis<LiveIntervals>();
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333
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334 TII = STI.getInstrInfo();
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335
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336 bool Changed = false;
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337
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338 if (DisableVSXFMAMutate)
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339 return Changed;
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340
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341 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
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342 MachineBasicBlock &B = *I++;
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343 if (processBlock(B))
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344 Changed = true;
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345 }
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346
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347 return Changed;
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348 }
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349
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350 void getAnalysisUsage(AnalysisUsage &AU) const override {
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351 AU.addRequired<LiveIntervals>();
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352 AU.addPreserved<LiveIntervals>();
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353 AU.addRequired<SlotIndexes>();
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354 AU.addPreserved<SlotIndexes>();
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355 MachineFunctionPass::getAnalysisUsage(AU);
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356 }
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357 };
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358 }
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359
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360 INITIALIZE_PASS_BEGIN(PPCVSXFMAMutate, DEBUG_TYPE,
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361 "PowerPC VSX FMA Mutation", false, false)
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362 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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363 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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364 INITIALIZE_PASS_END(PPCVSXFMAMutate, DEBUG_TYPE,
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365 "PowerPC VSX FMA Mutation", false, false)
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366
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367 char &llvm::PPCVSXFMAMutateID = PPCVSXFMAMutate::ID;
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368
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369 char PPCVSXFMAMutate::ID = 0;
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95
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370 FunctionPass *llvm::createPPCVSXFMAMutatePass() {
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371 return new PPCVSXFMAMutate();
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372 }
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