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1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 #include "SystemZTargetMachine.h"
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11 #include "SystemZTargetTransformInfo.h"
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12 #include "llvm/CodeGen/Passes.h"
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13 #include "llvm/Support/TargetRegistry.h"
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14 #include "llvm/Transforms/Scalar.h"
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15 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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16
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17 using namespace llvm;
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18
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19 extern cl::opt<bool> MISchedPostRA;
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20 extern "C" void LLVMInitializeSystemZTarget() {
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21 // Register the target.
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22 RegisterTargetMachine<SystemZTargetMachine> X(TheSystemZTarget);
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23 }
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24
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25 // Determine whether we use the vector ABI.
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26 static bool UsesVectorABI(StringRef CPU, StringRef FS) {
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27 // We use the vector ABI whenever the vector facility is avaiable.
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28 // This is the case by default if CPU is z13 or later, and can be
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29 // overridden via "[+-]vector" feature string elements.
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30 bool VectorABI = true;
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31 if (CPU.empty() || CPU == "generic" ||
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32 CPU == "z10" || CPU == "z196" || CPU == "zEC12")
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33 VectorABI = false;
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34
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35 SmallVector<StringRef, 3> Features;
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36 FS.split(Features, ',', -1, false /* KeepEmpty */);
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37 for (auto &Feature : Features) {
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38 if (Feature == "vector" || Feature == "+vector")
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39 VectorABI = true;
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40 if (Feature == "-vector")
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41 VectorABI = false;
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42 }
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43
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44 return VectorABI;
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45 }
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46
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47 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
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48 StringRef FS) {
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49 bool VectorABI = UsesVectorABI(CPU, FS);
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50 std::string Ret = "";
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51
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52 // Big endian.
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53 Ret += "E";
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54
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55 // Data mangling.
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56 Ret += DataLayout::getManglingComponent(TT);
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57
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58 // Make sure that global data has at least 16 bits of alignment by
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59 // default, so that we can refer to it using LARL. We don't have any
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60 // special requirements for stack variables though.
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61 Ret += "-i1:8:16-i8:8:16";
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62
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63 // 64-bit integers are naturally aligned.
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64 Ret += "-i64:64";
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65
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66 // 128-bit floats are aligned only to 64 bits.
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67 Ret += "-f128:64";
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68
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69 // When using the vector ABI, 128-bit vectors are also aligned to 64 bits.
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70 if (VectorABI)
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71 Ret += "-v128:64";
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72
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73 // We prefer 16 bits of aligned for all globals; see above.
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74 Ret += "-a:8:16";
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75
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76 // Integer registers are 32 or 64 bits.
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77 Ret += "-n32:64";
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78
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79 return Ret;
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80 }
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81
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82 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
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83 StringRef CPU, StringRef FS,
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84 const TargetOptions &Options,
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85 Reloc::Model RM, CodeModel::Model CM,
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86 CodeGenOpt::Level OL)
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87 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
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88 RM, CM, OL),
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89 TLOF(make_unique<TargetLoweringObjectFileELF>()),
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90 Subtarget(TT, CPU, FS, *this) {
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91 initAsmInfo();
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92 }
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93
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94 SystemZTargetMachine::~SystemZTargetMachine() {}
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95
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96 namespace {
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97 /// SystemZ Code Generator Pass Configuration Options.
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98 class SystemZPassConfig : public TargetPassConfig {
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99 public:
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100 SystemZPassConfig(SystemZTargetMachine *TM, PassManagerBase &PM)
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101 : TargetPassConfig(TM, PM) {}
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102
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103 SystemZTargetMachine &getSystemZTargetMachine() const {
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104 return getTM<SystemZTargetMachine>();
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105 }
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106
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107 void addIRPasses() override;
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108 bool addInstSelector() override;
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109 void addPreSched2() override;
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110 void addPreEmitPass() override;
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111 };
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112 } // end anonymous namespace
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113
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114 void SystemZPassConfig::addIRPasses() {
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115 TargetPassConfig::addIRPasses();
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116 }
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117
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118 bool SystemZPassConfig::addInstSelector() {
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119 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
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120
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121 if (getOptLevel() != CodeGenOpt::None)
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122 addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
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123
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124 return false;
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125 }
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126
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127 void SystemZPassConfig::addPreSched2() {
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128 if (getOptLevel() != CodeGenOpt::None &&
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129 getSystemZTargetMachine().getSubtargetImpl()->hasLoadStoreOnCond())
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130 addPass(&IfConverterID);
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131 }
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132
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133 void SystemZPassConfig::addPreEmitPass() {
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134
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135 // Do instruction shortening before compare elimination because some
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136 // vector instructions will be shortened into opcodes that compare
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137 // elimination recognizes.
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138 if (getOptLevel() != CodeGenOpt::None)
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139 addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
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140
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141 // We eliminate comparisons here rather than earlier because some
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142 // transformations can change the set of available CC values and we
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143 // generally want those transformations to have priority. This is
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144 // especially true in the commonest case where the result of the comparison
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145 // is used by a single in-range branch instruction, since we will then
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146 // be able to fuse the compare and the branch instead.
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147 //
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148 // For example, two-address NILF can sometimes be converted into
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149 // three-address RISBLG. NILF produces a CC value that indicates whether
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150 // the low word is zero, but RISBLG does not modify CC at all. On the
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151 // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
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152 // The CC value produced by NILL isn't useful for our purposes, but the
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153 // value produced by RISBG can be used for any comparison with zero
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154 // (not just equality). So there are some transformations that lose
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155 // CC values (while still being worthwhile) and others that happen to make
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156 // the CC result more useful than it was originally.
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157 //
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158 // Another reason is that we only want to use BRANCH ON COUNT in cases
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159 // where we know that the count register is not going to be spilled.
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160 //
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161 // Doing it so late makes it more likely that a register will be reused
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162 // between the comparison and the branch, but it isn't clear whether
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163 // preventing that would be a win or not.
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164 if (getOptLevel() != CodeGenOpt::None)
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165 addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
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166 addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
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167
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168 // Do final scheduling after all other optimizations, to get an
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169 // optimal input for the decoder (branch relaxation must happen
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170 // after block placement).
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171 if (getOptLevel() != CodeGenOpt::None) {
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172 if (MISchedPostRA)
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173 addPass(&PostMachineSchedulerID);
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174 else
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175 addPass(&PostRASchedulerID);
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176 }
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177 }
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178
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179 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
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180 return new SystemZPassConfig(this, PM);
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181 }
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182
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183 TargetIRAnalysis SystemZTargetMachine::getTargetIRAnalysis() {
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184 return TargetIRAnalysis([this](const Function &F) {
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185 return TargetTransformInfo(SystemZTTIImpl(this, F));
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186 });
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187 }
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