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annotate test/CodeGen/AArch64/regress-tblgen-chains.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s
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3 ; When generating DAG selection tables, TableGen used to only flag an
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4 ; instruction as needing a chain on its own account if it had a built-in pattern
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5 ; which used the chain. This meant that the AArch64 load/stores weren't
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6 ; recognised and so both loads from %locvar below were coalesced into a single
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7 ; LS8_LDR instruction (same operands other than the non-existent chain) and the
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8 ; increment was lost at return.
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10 ; This was obviously a Bad Thing.
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12 declare void @bar(i8*)
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14 define i64 @test_chains() {
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15 ; CHECK-LABEL: test_chains:
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16
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17 %locvar = alloca i8
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18
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19 call void @bar(i8* %locvar)
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54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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20 ; CHECK: bl {{_?bar}}
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afa8332a0e37 LLVM 3.8
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22 %inc.1 = load i8, i8* %locvar
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23 %inc.2 = zext i8 %inc.1 to i64
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24 %inc.3 = add i64 %inc.2, 1
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25 %inc.4 = trunc i64 %inc.3 to i8
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26 store i8 %inc.4, i8* %locvar
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54457678186b LLVM 3.6
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28 ; CHECK: ldurb {{w[0-9]+}}, [x29, [[LOCADDR:#-?[0-9]+]]]
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29 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #1
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30 ; CHECK: sturb w[[STRVAL:[0-9]+]], [x29, [[LOCADDR]]]
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31 ; CHECK; and w0, w[[STRVAL]], #0xff
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33 %ret.1 = load i8, i8* %locvar
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34 %ret.2 = zext i8 %ret.1 to i64
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35 ret i64 %ret.2
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36 ; CHECK: ret
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37 }