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annotate test/CodeGen/AMDGPU/store-barrier.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck --check-prefix=CHECK %s
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2 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck --check-prefix=CHECK %s
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4 ; This test is for a bug in the machine scheduler where stores without
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5 ; an underlying object would be moved across the barrier. In this
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6 ; test, the <2 x i8> store will be split into two i8 stores, so they
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7 ; won't have an underlying object.
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8
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9 ; CHECK-LABEL: {{^}}test:
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10 ; CHECK: ds_write_b8
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11 ; CHECK: ds_write_b8
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12 ; CHECK: s_barrier
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13 ; CHECK: s_endpgm
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14 ; Function Attrs: nounwind
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15 define void @test(<2 x i8> addrspace(3)* nocapture %arg, <2 x i8> addrspace(1)* nocapture readonly %arg1, i32 addrspace(1)* nocapture readonly %arg2, <2 x i8> addrspace(1)* nocapture %arg3, i32 %arg4, i64 %tmp9) {
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16 bb:
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17 %tmp10 = getelementptr inbounds i32, i32 addrspace(1)* %arg2, i64 %tmp9
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18 %tmp13 = load i32, i32 addrspace(1)* %tmp10, align 2
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19 %tmp14 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(3)* %arg, i32 %tmp13
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20 %tmp15 = load <2 x i8>, <2 x i8> addrspace(3)* %tmp14, align 2
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21 %tmp16 = add i32 %tmp13, 1
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22 %tmp17 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(3)* %arg, i32 %tmp16
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23 store <2 x i8> %tmp15, <2 x i8> addrspace(3)* %tmp17, align 2
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24 tail call void @llvm.AMDGPU.barrier.local() #2
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25 %tmp25 = load i32, i32 addrspace(1)* %tmp10, align 4
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26 %tmp26 = sext i32 %tmp25 to i64
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27 %tmp27 = sext i32 %arg4 to i64
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28 %tmp28 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(3)* %arg, i32 %tmp25, i32 %arg4
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29 %tmp29 = load i8, i8 addrspace(3)* %tmp28, align 1
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30 %tmp30 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(1)* %arg3, i64 %tmp26, i64 %tmp27
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31 store i8 %tmp29, i8 addrspace(1)* %tmp30, align 1
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32 %tmp32 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(3)* %arg, i32 %tmp25, i32 0
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33 %tmp33 = load i8, i8 addrspace(3)* %tmp32, align 1
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34 %tmp35 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(1)* %arg3, i64 %tmp26, i64 0
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35 store i8 %tmp33, i8 addrspace(1)* %tmp35, align 1
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36 ret void
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37 }
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39 ; Function Attrs: convergent nounwind
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40 declare void @llvm.AMDGPU.barrier.local() #2
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42 attributes #2 = { convergent nounwind }