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annotate test/CodeGen/X86/atomic-flags.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children
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afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs | FileCheck %s
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2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -verify-machineinstrs | FileCheck %s
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3
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4 ; Make sure that flags are properly preserved despite atomic optimizations.
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5
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6 define i32 @atomic_and_flags_1(i8* %p, i32 %a, i32 %b) {
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7 ; CHECK-LABEL: atomic_and_flags_1:
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8
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9 ; Generate flags value, and use it.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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10 ; CHECK: cmpl
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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11 ; CHECK-NEXT: jne
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12 %cmp = icmp eq i32 %a, %b
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13 br i1 %cmp, label %L1, label %L2
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14
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15 L1:
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16 ; The following pattern will get folded.
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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17 ; CHECK: incb
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18 %1 = load atomic i8, i8* %p seq_cst, align 1
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19 %2 = add i8 %1, 1 ; This forces the INC instruction to be generated.
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20 store atomic i8 %2, i8* %p release, align 1
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21
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22 ; Use the comparison result again. We need to rematerialize the comparison
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23 ; somehow. This test checks that cmpl gets emitted again, but any
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24 ; rematerialization would work (the optimizer used to clobber the flags with
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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25 ; the add).
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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26 ; CHECK-NEXT: cmpl
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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27 ; CHECK-NEXT: jne
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28 br i1 %cmp, label %L3, label %L4
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29
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30 L2:
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31 ret i32 2
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32
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33 L3:
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34 ret i32 3
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35
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36 L4:
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37 ret i32 4
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38 }
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39
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parents: 95
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40 ; Same as above, but using 2 as immediate to avoid the INC instruction.
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41 define i32 @atomic_and_flags_2(i8* %p, i32 %a, i32 %b) {
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parents: 95
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42 ; CHECK-LABEL: atomic_and_flags_2:
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parents: 95
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43 ; CHECK: cmpl
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parents: 95
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44 ; CHECK-NEXT: jne
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parents: 95
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45 %cmp = icmp eq i32 %a, %b
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parents: 95
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46 br i1 %cmp, label %L1, label %L2
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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47 L1:
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parents: 95
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48 ; CHECK: addb
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parents: 95
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49 %1 = load atomic i8, i8* %p seq_cst, align 1
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parents: 95
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50 %2 = add i8 %1, 2
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parents: 95
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51 store atomic i8 %2, i8* %p release, align 1
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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52 ; CHECK-NEXT: cmpl
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parents: 95
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53 ; CHECK-NEXT: jne
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parents: 95
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54 br i1 %cmp, label %L3, label %L4
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parents: 95
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55 L2:
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parents: 95
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56 ret i32 2
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parents: 95
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57 L3:
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parents: 95
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58 ret i32 3
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parents: 95
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59 L4:
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parents: 95
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60 ret i32 4
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parents: 95
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61 }