annotate lib/CodeGen/BranchRelaxation.cpp @ 121:803732b1fca8

LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children 3a76565eade5
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1 //===- BranchRelaxation.cpp -----------------------------------------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 #include "llvm/ADT/SmallVector.h"
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11 #include "llvm/ADT/Statistic.h"
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12 #include "llvm/CodeGen/LivePhysRegs.h"
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13 #include "llvm/CodeGen/MachineBasicBlock.h"
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14 #include "llvm/CodeGen/MachineFunction.h"
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15 #include "llvm/CodeGen/MachineFunctionPass.h"
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16 #include "llvm/CodeGen/MachineInstr.h"
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17 #include "llvm/CodeGen/RegisterScavenging.h"
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18 #include "llvm/IR/DebugLoc.h"
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19 #include "llvm/Pass.h"
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20 #include "llvm/Support/Compiler.h"
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21 #include "llvm/Support/Debug.h"
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22 #include "llvm/Support/Format.h"
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23 #include "llvm/Support/MathExtras.h"
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24 #include "llvm/Support/raw_ostream.h"
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25 #include "llvm/Target/TargetInstrInfo.h"
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26 #include "llvm/Target/TargetRegisterInfo.h"
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27 #include "llvm/Target/TargetSubtargetInfo.h"
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28 #include <cassert>
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29 #include <cstdint>
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30 #include <iterator>
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31 #include <memory>
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32
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33 using namespace llvm;
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34
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35 #define DEBUG_TYPE "branch-relaxation"
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36
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37 STATISTIC(NumSplit, "Number of basic blocks split");
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38 STATISTIC(NumConditionalRelaxed, "Number of conditional branches relaxed");
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39 STATISTIC(NumUnconditionalRelaxed, "Number of unconditional branches relaxed");
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40
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41 #define BRANCH_RELAX_NAME "Branch relaxation pass"
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42
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43 namespace {
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44
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45 class BranchRelaxation : public MachineFunctionPass {
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46 /// BasicBlockInfo - Information about the offset and size of a single
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47 /// basic block.
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48 struct BasicBlockInfo {
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49 /// Offset - Distance from the beginning of the function to the beginning
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50 /// of this basic block.
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51 ///
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52 /// The offset is always aligned as required by the basic block.
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53 unsigned Offset = 0;
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54
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55 /// Size - Size of the basic block in bytes. If the block contains
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56 /// inline assembly, this is a worst case estimate.
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57 ///
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58 /// The size does not include any alignment padding whether from the
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59 /// beginning of the block, or from an aligned jump table at the end.
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60 unsigned Size = 0;
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61
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62 BasicBlockInfo() = default;
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63
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64 /// Compute the offset immediately following this block. \p MBB is the next
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65 /// block.
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66 unsigned postOffset(const MachineBasicBlock &MBB) const {
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67 unsigned PO = Offset + Size;
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68 unsigned Align = MBB.getAlignment();
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69 if (Align == 0)
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70 return PO;
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71
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72 unsigned AlignAmt = 1 << Align;
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73 unsigned ParentAlign = MBB.getParent()->getAlignment();
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74 if (Align <= ParentAlign)
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75 return PO + OffsetToAlignment(PO, AlignAmt);
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76
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77 // The alignment of this MBB is larger than the function's alignment, so we
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78 // can't tell whether or not it will insert nops. Assume that it will.
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79 return PO + AlignAmt + OffsetToAlignment(PO, AlignAmt);
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80 }
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81 };
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82
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83 SmallVector<BasicBlockInfo, 16> BlockInfo;
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84 std::unique_ptr<RegScavenger> RS;
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85 LivePhysRegs LiveRegs;
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86
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87 MachineFunction *MF;
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88 const TargetRegisterInfo *TRI;
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89 const TargetInstrInfo *TII;
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90
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91 bool relaxBranchInstructions();
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92 void scanFunction();
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93
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94 MachineBasicBlock *createNewBlockAfter(MachineBasicBlock &BB);
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95
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96 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr &MI,
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97 MachineBasicBlock *DestBB);
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98 void adjustBlockOffsets(MachineBasicBlock &MBB);
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99 bool isBlockInRange(const MachineInstr &MI, const MachineBasicBlock &BB) const;
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100
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101 bool fixupConditionalBranch(MachineInstr &MI);
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102 bool fixupUnconditionalBranch(MachineInstr &MI);
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103 uint64_t computeBlockSize(const MachineBasicBlock &MBB) const;
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104 unsigned getInstrOffset(const MachineInstr &MI) const;
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105 void dumpBBs();
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106 void verify();
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107
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108 public:
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109 static char ID;
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110
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111 BranchRelaxation() : MachineFunctionPass(ID) {}
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112
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113 bool runOnMachineFunction(MachineFunction &MF) override;
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114
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115 StringRef getPassName() const override { return BRANCH_RELAX_NAME; }
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116 };
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117
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118 } // end anonymous namespace
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119
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120 char BranchRelaxation::ID = 0;
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121
120
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122 char &llvm::BranchRelaxationPassID = BranchRelaxation::ID;
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123
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124 INITIALIZE_PASS(BranchRelaxation, DEBUG_TYPE, BRANCH_RELAX_NAME, false, false)
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125
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126 /// verify - check BBOffsets, BBSizes, alignment of islands
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127 void BranchRelaxation::verify() {
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128 #ifndef NDEBUG
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129 unsigned PrevNum = MF->begin()->getNumber();
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130 for (MachineBasicBlock &MBB : *MF) {
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131 unsigned Align = MBB.getAlignment();
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132 unsigned Num = MBB.getNumber();
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133 assert(BlockInfo[Num].Offset % (1u << Align) == 0);
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134 assert(!Num || BlockInfo[PrevNum].postOffset(MBB) <= BlockInfo[Num].Offset);
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135 assert(BlockInfo[Num].Size == computeBlockSize(MBB));
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136 PrevNum = Num;
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137 }
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138 #endif
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139 }
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140
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141 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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142 /// print block size and offset information - debugging
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143 LLVM_DUMP_METHOD void BranchRelaxation::dumpBBs() {
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144 for (auto &MBB : *MF) {
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145 const BasicBlockInfo &BBI = BlockInfo[MBB.getNumber()];
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146 dbgs() << format("BB#%u\toffset=%08x\t", MBB.getNumber(), BBI.Offset)
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147 << format("size=%#x\n", BBI.Size);
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148 }
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149 }
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150 #endif
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151
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152 /// scanFunction - Do the initial scan of the function, building up
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153 /// information about each block.
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154 void BranchRelaxation::scanFunction() {
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155 BlockInfo.clear();
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156 BlockInfo.resize(MF->getNumBlockIDs());
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157
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158 // First thing, compute the size of all basic blocks, and see if the function
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159 // has any inline assembly in it. If so, we have to be conservative about
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160 // alignment assumptions, as we don't know for sure the size of any
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161 // instructions in the inline assembly.
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162 for (MachineBasicBlock &MBB : *MF)
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163 BlockInfo[MBB.getNumber()].Size = computeBlockSize(MBB);
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164
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165 // Compute block offsets and known bits.
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166 adjustBlockOffsets(*MF->begin());
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167 }
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168
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169 /// computeBlockSize - Compute the size for MBB.
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170 uint64_t BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) const {
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171 uint64_t Size = 0;
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172 for (const MachineInstr &MI : MBB)
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173 Size += TII->getInstSizeInBytes(MI);
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174 return Size;
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175 }
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176
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177 /// getInstrOffset - Return the current offset of the specified machine
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178 /// instruction from the start of the function. This offset changes as stuff is
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179 /// moved around inside the function.
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180 unsigned BranchRelaxation::getInstrOffset(const MachineInstr &MI) const {
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181 const MachineBasicBlock *MBB = MI.getParent();
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182
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183 // The offset is composed of two things: the sum of the sizes of all MBB's
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184 // before this instruction's block, and the offset from the start of the block
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185 // it is in.
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186 unsigned Offset = BlockInfo[MBB->getNumber()].Offset;
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187
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188 // Sum instructions before MI in MBB.
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189 for (MachineBasicBlock::const_iterator I = MBB->begin(); &*I != &MI; ++I) {
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190 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
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191 Offset += TII->getInstSizeInBytes(*I);
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192 }
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193
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194 return Offset;
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195 }
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196
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197 void BranchRelaxation::adjustBlockOffsets(MachineBasicBlock &Start) {
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198 unsigned PrevNum = Start.getNumber();
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199 for (auto &MBB : make_range(MachineFunction::iterator(Start), MF->end())) {
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200 unsigned Num = MBB.getNumber();
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201 if (!Num) // block zero is never changed from offset zero.
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202 continue;
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203 // Get the offset and known bits at the end of the layout predecessor.
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204 // Include the alignment of the current block.
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205 BlockInfo[Num].Offset = BlockInfo[PrevNum].postOffset(MBB);
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206
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207 PrevNum = Num;
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208 }
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209 }
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210
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211 /// Insert a new empty basic block and insert it after \BB
120
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212 MachineBasicBlock *BranchRelaxation::createNewBlockAfter(MachineBasicBlock &BB) {
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213 // Create a new MBB for the code after the OrigBB.
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214 MachineBasicBlock *NewBB =
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215 MF->CreateMachineBasicBlock(BB.getBasicBlock());
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216 MF->insert(++BB.getIterator(), NewBB);
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217
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218 // Insert an entry into BlockInfo to align it properly with the block numbers.
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219 BlockInfo.insert(BlockInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
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220
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221 return NewBB;
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222 }
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223
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224 /// Split the basic block containing MI into two blocks, which are joined by
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225 /// an unconditional branch. Update data structures and renumber blocks to
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226 /// account for this change and returns the newly created block.
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227 MachineBasicBlock *BranchRelaxation::splitBlockBeforeInstr(MachineInstr &MI,
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228 MachineBasicBlock *DestBB) {
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229 MachineBasicBlock *OrigBB = MI.getParent();
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230
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231 // Create a new MBB for the code after the OrigBB.
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232 MachineBasicBlock *NewBB =
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233 MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
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234 MF->insert(++OrigBB->getIterator(), NewBB);
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235
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236 // Splice the instructions starting with MI over to NewBB.
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237 NewBB->splice(NewBB->end(), OrigBB, MI.getIterator(), OrigBB->end());
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238
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239 // Add an unconditional branch from OrigBB to NewBB.
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240 // Note the new unconditional branch is not being recorded.
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241 // There doesn't seem to be meaningful DebugInfo available; this doesn't
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242 // correspond to anything in the source.
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243 TII->insertUnconditionalBranch(*OrigBB, NewBB, DebugLoc());
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244
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245 // Insert an entry into BlockInfo to align it properly with the block numbers.
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246 BlockInfo.insert(BlockInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
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247
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248 NewBB->transferSuccessors(OrigBB);
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249 OrigBB->addSuccessor(NewBB);
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250 OrigBB->addSuccessor(DestBB);
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251
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252 // Cleanup potential unconditional branch to successor block.
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253 // Note that updateTerminator may change the size of the blocks.
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254 NewBB->updateTerminator();
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255 OrigBB->updateTerminator();
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256
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257 // Figure out how large the OrigBB is. As the first half of the original
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258 // block, it cannot contain a tablejump. The size includes
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259 // the new jump we added. (It should be possible to do this without
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260 // recounting everything, but it's very confusing, and this is rarely
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261 // executed.)
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262 BlockInfo[OrigBB->getNumber()].Size = computeBlockSize(*OrigBB);
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263
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264 // Figure out how large the NewMBB is. As the second half of the original
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265 // block, it may contain a tablejump.
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266 BlockInfo[NewBB->getNumber()].Size = computeBlockSize(*NewBB);
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267
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268 // All BBOffsets following these blocks must be modified.
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269 adjustBlockOffsets(*OrigBB);
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270
121
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diff changeset
271 // Need to fix live-in lists if we track liveness.
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diff changeset
272 if (TRI->trackLivenessAfterRegAlloc(*MF))
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diff changeset
273 computeAndAddLiveIns(LiveRegs, *NewBB);
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diff changeset
274
120
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275 ++NumSplit;
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276
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277 return NewBB;
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278 }
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279
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280 /// isBlockInRange - Returns true if the distance between specific MI and
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281 /// specific BB can fit in MI's displacement field.
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diff changeset
282 bool BranchRelaxation::isBlockInRange(
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parents:
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283 const MachineInstr &MI, const MachineBasicBlock &DestBB) const {
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diff changeset
284 int64_t BrOffset = getInstrOffset(MI);
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285 int64_t DestOffset = BlockInfo[DestBB.getNumber()].Offset;
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286
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287 if (TII->isBranchOffsetInRange(MI.getOpcode(), DestOffset - BrOffset))
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parents:
diff changeset
288 return true;
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289
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parents:
diff changeset
290 DEBUG(
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
291 dbgs() << "Out of range branch to destination BB#" << DestBB.getNumber()
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parents:
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292 << " from BB#" << MI.getParent()->getNumber()
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parents:
diff changeset
293 << " to " << DestOffset
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parents:
diff changeset
294 << " offset " << DestOffset - BrOffset
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parents:
diff changeset
295 << '\t' << MI
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parents:
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296 );
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parents:
diff changeset
297
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parents:
diff changeset
298 return false;
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parents:
diff changeset
299 }
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parents:
diff changeset
300
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parents:
diff changeset
301 /// fixupConditionalBranch - Fix up a conditional branch whose destination is
1172e4bd9c6f update 4.0.0
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parents:
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302 /// too far away to fit in its displacement field. It is converted to an inverse
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parents:
diff changeset
303 /// conditional branch + an unconditional branch to the destination.
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parents:
diff changeset
304 bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
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parents:
diff changeset
305 DebugLoc DL = MI.getDebugLoc();
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parents:
diff changeset
306 MachineBasicBlock *MBB = MI.getParent();
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parents:
diff changeset
307 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
308 SmallVector<MachineOperand, 4> Cond;
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parents:
diff changeset
309
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parents:
diff changeset
310 bool Fail = TII->analyzeBranch(*MBB, TBB, FBB, Cond);
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parents:
diff changeset
311 assert(!Fail && "branches to be relaxed must be analyzable");
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parents:
diff changeset
312 (void)Fail;
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parents:
diff changeset
313
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parents:
diff changeset
314 // Add an unconditional branch to the destination and invert the branch
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parents:
diff changeset
315 // condition to jump over it:
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parents:
diff changeset
316 // tbz L1
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parents:
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317 // =>
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parents:
diff changeset
318 // tbnz L2
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parents:
diff changeset
319 // b L1
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parents:
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320 // L2:
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
321
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parents:
diff changeset
322 if (FBB && isBlockInRange(MI, *FBB)) {
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
323 // Last MI in the BB is an unconditional branch. We can simply invert the
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
324 // condition and swap destinations:
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
325 // beq L1
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parents:
diff changeset
326 // b L2
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parents:
diff changeset
327 // =>
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parents:
diff changeset
328 // bne L2
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parents:
diff changeset
329 // b L1
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parents:
diff changeset
330 DEBUG(dbgs() << " Invert condition and swap "
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
331 "its destination with " << MBB->back());
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
332
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parents:
diff changeset
333 TII->reverseBranchCondition(Cond);
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parents:
diff changeset
334 int OldSize = 0, NewSize = 0;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
335 TII->removeBranch(*MBB, &OldSize);
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
336 TII->insertBranch(*MBB, FBB, TBB, Cond, DL, &NewSize);
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
337
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parents:
diff changeset
338 BlockInfo[MBB->getNumber()].Size += (NewSize - OldSize);
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
339 return true;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
340 } else if (FBB) {
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
341 // We need to split the basic block here to obtain two long-range
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
342 // unconditional branches.
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parents:
diff changeset
343 auto &NewBB = *MF->CreateMachineBasicBlock(MBB->getBasicBlock());
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parents:
diff changeset
344 MF->insert(++MBB->getIterator(), &NewBB);
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
345
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parents:
diff changeset
346 // Insert an entry into BlockInfo to align it properly with the block
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parents:
diff changeset
347 // numbers.
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parents:
diff changeset
348 BlockInfo.insert(BlockInfo.begin() + NewBB.getNumber(), BasicBlockInfo());
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parents:
diff changeset
349
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parents:
diff changeset
350 unsigned &NewBBSize = BlockInfo[NewBB.getNumber()].Size;
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parents:
diff changeset
351 int NewBrSize;
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parents:
diff changeset
352 TII->insertUnconditionalBranch(NewBB, FBB, DL, &NewBrSize);
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
353 NewBBSize += NewBrSize;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
354
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
355 // Update the successor lists according to the transformation to follow.
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parents:
diff changeset
356 // Do it here since if there's no split, no update is needed.
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parents:
diff changeset
357 MBB->replaceSuccessor(FBB, &NewBB);
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parents:
diff changeset
358 NewBB.addSuccessor(FBB);
121
803732b1fca8 LLVM 5.0
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parents: 120
diff changeset
359
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parents: 120
diff changeset
360 // Need to fix live-in lists if we track liveness.
803732b1fca8 LLVM 5.0
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parents: 120
diff changeset
361 if (TRI->trackLivenessAfterRegAlloc(*MF))
803732b1fca8 LLVM 5.0
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parents: 120
diff changeset
362 computeAndAddLiveIns(LiveRegs, NewBB);
120
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
363 }
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
364
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parents:
diff changeset
365 // We now have an appropriate fall-through block in place (either naturally or
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
366 // just created), so we can invert the condition.
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
367 MachineBasicBlock &NextBB = *std::next(MachineFunction::iterator(MBB));
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parents:
diff changeset
368
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parents:
diff changeset
369 DEBUG(dbgs() << " Insert B to BB#" << TBB->getNumber()
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
370 << ", invert condition and change dest. to BB#"
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
371 << NextBB.getNumber() << '\n');
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parents:
diff changeset
372
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parents:
diff changeset
373 unsigned &MBBSize = BlockInfo[MBB->getNumber()].Size;
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parents:
diff changeset
374
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parents:
diff changeset
375 // Insert a new conditional branch and a new unconditional branch.
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parents:
diff changeset
376 int RemovedSize = 0;
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parents:
diff changeset
377 TII->reverseBranchCondition(Cond);
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parents:
diff changeset
378 TII->removeBranch(*MBB, &RemovedSize);
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parents:
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379 MBBSize -= RemovedSize;
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parents:
diff changeset
380
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parents:
diff changeset
381 int AddedSize = 0;
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parents:
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382 TII->insertBranch(*MBB, &NextBB, TBB, Cond, DL, &AddedSize);
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parents:
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383 MBBSize += AddedSize;
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parents:
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384
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parents:
diff changeset
385 // Finally, keep the block offsets up to date.
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parents:
diff changeset
386 adjustBlockOffsets(*MBB);
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parents:
diff changeset
387 return true;
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parents:
diff changeset
388 }
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parents:
diff changeset
389
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parents:
diff changeset
390 bool BranchRelaxation::fixupUnconditionalBranch(MachineInstr &MI) {
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parents:
diff changeset
391 MachineBasicBlock *MBB = MI.getParent();
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parents:
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392
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parents:
diff changeset
393 unsigned OldBrSize = TII->getInstSizeInBytes(MI);
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parents:
diff changeset
394 MachineBasicBlock *DestBB = TII->getBranchDestBlock(MI);
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parents:
diff changeset
395
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parents:
diff changeset
396 int64_t DestOffset = BlockInfo[DestBB->getNumber()].Offset;
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parents:
diff changeset
397 int64_t SrcOffset = getInstrOffset(MI);
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parents:
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398
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parents:
diff changeset
399 assert(!TII->isBranchOffsetInRange(MI.getOpcode(), DestOffset - SrcOffset));
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parents:
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400
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parents:
diff changeset
401 BlockInfo[MBB->getNumber()].Size -= OldBrSize;
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parents:
diff changeset
402
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parents:
diff changeset
403 MachineBasicBlock *BranchBB = MBB;
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parents:
diff changeset
404
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parents:
diff changeset
405 // If this was an expanded conditional branch, there is already a single
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parents:
diff changeset
406 // unconditional branch in a block.
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parents:
diff changeset
407 if (!MBB->empty()) {
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parents:
diff changeset
408 BranchBB = createNewBlockAfter(*MBB);
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parents:
diff changeset
409
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parents:
diff changeset
410 // Add live outs.
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parents:
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411 for (const MachineBasicBlock *Succ : MBB->successors()) {
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parents:
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412 for (const MachineBasicBlock::RegisterMaskPair &LiveIn : Succ->liveins())
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parents:
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413 BranchBB->addLiveIn(LiveIn);
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parents:
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414 }
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parents:
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415
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parents:
diff changeset
416 BranchBB->sortUniqueLiveIns();
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parents:
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417 BranchBB->addSuccessor(DestBB);
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parents:
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418 MBB->replaceSuccessor(DestBB, BranchBB);
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parents:
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419 }
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parents:
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420
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parents:
diff changeset
421 DebugLoc DL = MI.getDebugLoc();
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parents:
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422 MI.eraseFromParent();
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parents:
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423 BlockInfo[BranchBB->getNumber()].Size += TII->insertIndirectBranch(
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parents:
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424 *BranchBB, *DestBB, DL, DestOffset - SrcOffset, RS.get());
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parents:
diff changeset
425
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parents:
diff changeset
426 adjustBlockOffsets(*MBB);
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parents:
diff changeset
427 return true;
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parents:
diff changeset
428 }
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parents:
diff changeset
429
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parents:
diff changeset
430 bool BranchRelaxation::relaxBranchInstructions() {
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parents:
diff changeset
431 bool Changed = false;
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parents:
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432
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parents:
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433 // Relaxing branches involves creating new basic blocks, so re-eval
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parents:
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434 // end() for termination.
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parents:
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435 for (MachineFunction::iterator I = MF->begin(); I != MF->end(); ++I) {
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parents:
diff changeset
436 MachineBasicBlock &MBB = *I;
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parents:
diff changeset
437
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
438 // Empty block?
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
439 MachineBasicBlock::iterator Last = MBB.getLastNonDebugInstr();
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
440 if (Last == MBB.end())
120
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parents:
diff changeset
441 continue;
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parents:
diff changeset
442
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parents:
diff changeset
443 // Expand the unconditional branch first if necessary. If there is a
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
444 // conditional branch, this will end up changing the branch destination of
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
445 // it to be over the newly inserted indirect branch block, which may avoid
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
446 // the need to try expanding the conditional branch first, saving an extra
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
447 // jump.
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parents:
diff changeset
448 if (Last->isUnconditionalBranch()) {
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parents:
diff changeset
449 // Unconditional branch destination might be unanalyzable, assume these
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
450 // are OK.
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parents:
diff changeset
451 if (MachineBasicBlock *DestBB = TII->getBranchDestBlock(*Last)) {
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parents:
diff changeset
452 if (!isBlockInRange(*Last, *DestBB)) {
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
453 fixupUnconditionalBranch(*Last);
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
454 ++NumUnconditionalRelaxed;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
455 Changed = true;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
456 }
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
457 }
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
458 }
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
459
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parents:
diff changeset
460 // Loop over the conditional branches.
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parents:
diff changeset
461 MachineBasicBlock::iterator Next;
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parents:
diff changeset
462 for (MachineBasicBlock::iterator J = MBB.getFirstTerminator();
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parents:
diff changeset
463 J != MBB.end(); J = Next) {
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
464 Next = std::next(J);
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parents:
diff changeset
465 MachineInstr &MI = *J;
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parents:
diff changeset
466
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parents:
diff changeset
467 if (MI.isConditionalBranch()) {
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parents:
diff changeset
468 MachineBasicBlock *DestBB = TII->getBranchDestBlock(MI);
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
469 if (!isBlockInRange(MI, *DestBB)) {
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
470 if (Next != MBB.end() && Next->isConditionalBranch()) {
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
471 // If there are multiple conditional branches, this isn't an
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
472 // analyzable block. Split later terminators into a new block so
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
473 // each one will be analyzable.
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
474
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
475 splitBlockBeforeInstr(*Next, DestBB);
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
476 } else {
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
477 fixupConditionalBranch(MI);
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
478 ++NumConditionalRelaxed;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
479 }
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
480
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
481 Changed = true;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
482
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
483 // This may have modified all of the terminators, so start over.
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
484 Next = MBB.getFirstTerminator();
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
485 }
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
486 }
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
487 }
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
488 }
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
489
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
490 return Changed;
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
491 }
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
492
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
493 bool BranchRelaxation::runOnMachineFunction(MachineFunction &mf) {
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
494 MF = &mf;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
495
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
496 DEBUG(dbgs() << "***** BranchRelaxation *****\n");
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
497
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
498 const TargetSubtargetInfo &ST = MF->getSubtarget();
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
499 TII = ST.getInstrInfo();
1172e4bd9c6f update 4.0.0
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parents:
diff changeset
500
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
501 TRI = ST.getRegisterInfo();
120
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
502 if (TRI->trackLivenessAfterRegAlloc(*MF))
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
503 RS.reset(new RegScavenger());
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
504
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
505 // Renumber all of the machine basic blocks in the function, guaranteeing that
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
506 // the numbers agree with the position of the block in the function.
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
507 MF->RenumberBlocks();
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
508
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
509 // Do the initial scan of the function, building up information about the
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
510 // sizes of each block.
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
511 scanFunction();
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
512
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
513 DEBUG(dbgs() << " Basic blocks before relaxation\n"; dumpBBs(););
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
514
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
515 bool MadeChange = false;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
516 while (relaxBranchInstructions())
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
517 MadeChange = true;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
518
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
519 // After a while, this might be made debug-only, but it is not expensive.
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
520 verify();
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
521
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
522 DEBUG(dbgs() << " Basic blocks after relaxation\n\n"; dumpBBs());
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
523
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
524 BlockInfo.clear();
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
525
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
526 return MadeChange;
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
527 }