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annotate lib/Target/Hexagon/HexagonIICScalar.td @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
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children c2174574ed3a
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121
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1 //===--- HexagonIICScalar.td ----------------------------------------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 // These itinerary class descriptions are based on the instruction timing
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11 // classes as per V62. Curretnly, they are just extracted from
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12 // HexagonScheduleV62.td but will soon be auto-generated by HexagonGen.py.
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13
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14 class PseudoItin {
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15 list<InstrItinData> PseudoItin_list = [
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16 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
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17 [1, 1, 1]>,
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18 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
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19 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
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20 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
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21 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
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22 ];
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23 }
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24
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25 class ScalarItin {
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26 list<InstrItinData> ScalarItin_list = [
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27 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
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28 [3, 1], [Hex_FWD, Hex_FWD]>,
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29 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
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30 [1, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>
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31 ];
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32 }