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annotate lib/Target/MSP430/MSP430InstrInfo.h @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children 3a76565eade5
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1 //===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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14 #ifndef LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
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15 #define LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
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16
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17 #include "MSP430RegisterInfo.h"
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18 #include "llvm/Target/TargetInstrInfo.h"
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19
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20 #define GET_INSTRINFO_HEADER
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21 #include "MSP430GenInstrInfo.inc"
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22
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23 namespace llvm {
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24
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25 class MSP430Subtarget;
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26
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27 /// MSP430II - This namespace holds all of the target specific flags that
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28 /// instruction info tracks.
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29 ///
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30 namespace MSP430II {
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31 enum {
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32 SizeShift = 2,
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33 SizeMask = 7 << SizeShift,
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34
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35 SizeUnknown = 0 << SizeShift,
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36 SizeSpecial = 1 << SizeShift,
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37 Size2Bytes = 2 << SizeShift,
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38 Size4Bytes = 3 << SizeShift,
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39 Size6Bytes = 4 << SizeShift
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40 };
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41 }
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42
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43 class MSP430InstrInfo : public MSP430GenInstrInfo {
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44 const MSP430RegisterInfo RI;
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45 virtual void anchor();
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46 public:
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47 explicit MSP430InstrInfo(MSP430Subtarget &STI);
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48
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49 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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50 /// such, whenever a client has an instance of instruction info, it should
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51 /// always be able to get register info as well (through this method).
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52 ///
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53 const TargetRegisterInfo &getRegisterInfo() const { return RI; }
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54
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55 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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56 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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57 bool KillSrc) const override;
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58
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59 void storeRegToStackSlot(MachineBasicBlock &MBB,
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60 MachineBasicBlock::iterator MI,
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61 unsigned SrcReg, bool isKill,
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62 int FrameIndex,
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63 const TargetRegisterClass *RC,
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64 const TargetRegisterInfo *TRI) const override;
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65 void loadRegFromStackSlot(MachineBasicBlock &MBB,
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66 MachineBasicBlock::iterator MI,
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67 unsigned DestReg, int FrameIdx,
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68 const TargetRegisterClass *RC,
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69 const TargetRegisterInfo *TRI) const override;
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71 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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72
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73 // Branch folding goodness
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74 bool
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75 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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76 bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
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77 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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78 MachineBasicBlock *&FBB,
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79 SmallVectorImpl<MachineOperand> &Cond,
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80 bool AllowModify) const override;
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81
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82 unsigned removeBranch(MachineBasicBlock &MBB,
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83 int *BytesRemoved = nullptr) const override;
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84 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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85 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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86 const DebugLoc &DL,
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87 int *BytesAdded = nullptr) const override;
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88
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89 int64_t getFramePoppedByCallee(const MachineInstr &I) const {
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90 assert(isFrameInstr(I) && "Not a frame instruction");
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91 assert(I.getOperand(1).getImm() >= 0 && "Size must not be negative");
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92 return I.getOperand(1).getImm();
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93 }
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94 };
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95
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96 }
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98 #endif