121
|
1 //===-- MipsMTInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
|
|
2 //
|
|
3 // The LLVM Compiler Infrastructure
|
|
4 //
|
|
5 // This file is distributed under the University of Illinois Open Source
|
|
6 // License. See LICENSE.TXT for details.
|
|
7 //
|
|
8 //===----------------------------------------------------------------------===//
|
|
9
|
|
10 //===----------------------------------------------------------------------===//
|
|
11 // Describe the MIPS MT instructions format
|
|
12 //
|
|
13 // opcode - operation code.
|
|
14 // rt - destination register
|
|
15 //
|
|
16 //===----------------------------------------------------------------------===//
|
|
17
|
|
18 class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
|
|
19 PredicateControl {
|
|
20 let DecoderNamespace = "Mips";
|
|
21 let EncodingPredicates = [HasStdEnc];
|
|
22 }
|
|
23
|
|
24 class OPCODE1<bits<1> Val> {
|
|
25 bits<1> Value = Val;
|
|
26 }
|
|
27
|
|
28 def OPCODE_SC_D : OPCODE1<0b0>;
|
|
29 def OPCODE_SC_E : OPCODE1<0b1>;
|
|
30
|
|
31 class FIELD5<bits<5> Val> {
|
|
32 bits<5> Value = Val;
|
|
33 }
|
|
34
|
|
35 def FIELD5_1_DMT_EMT : FIELD5<0b00001>;
|
|
36 def FIELD5_2_DMT_EMT : FIELD5<0b01111>;
|
|
37 def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;
|
|
38
|
|
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
|
|
40 bits<32> Inst;
|
|
41
|
|
42 bits<5> rt;
|
|
43 let Inst{31-26} = 0b010000; // COP0
|
|
44 let Inst{25-21} = 0b01011; // MFMC0
|
|
45 let Inst{20-16} = rt;
|
|
46 let Inst{15-11} = Op1.Value;
|
|
47 let Inst{10-6} = Op2.Value;
|
|
48 let Inst{5} = sc.Value;
|
|
49 let Inst{4-3} = 0b00;
|
|
50 let Inst{2-0} = 0b001;
|
|
51 }
|
|
52
|
|
53 class SPECIAL3_MT_FORK : MipsMTInst {
|
|
54 bits<32> Inst;
|
|
55
|
|
56 bits<5> rs;
|
|
57 bits<5> rt;
|
|
58 bits<5> rd;
|
|
59 let Inst{31-26} = 0b011111; // SPECIAL3
|
|
60 let Inst{25-21} = rs;
|
|
61 let Inst{20-16} = rt;
|
|
62 let Inst{15-11} = rd;
|
|
63 let Inst{10-6} = 0b00000;
|
|
64 let Inst{5-0} = 0b001000; // FORK
|
|
65 }
|
|
66
|
|
67 class SPECIAL3_MT_YIELD : MipsMTInst {
|
|
68 bits<32> Inst;
|
|
69
|
|
70 bits<5> rs;
|
|
71 bits<5> rd;
|
|
72 let Inst{31-26} = 0b011111; // SPECIAL3
|
|
73 let Inst{25-21} = rs;
|
|
74 let Inst{20-16} = 0b00000;
|
|
75 let Inst{15-11} = rd;
|
|
76 let Inst{10-6} = 0b00000;
|
|
77 let Inst{5-0} = 0b001001; // FORK
|
|
78 }
|