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annotate lib/Target/Mips/MipsOptionRecord.h @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents afa8332a0e37
children c2174574ed3a
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1 //===- MipsOptionRecord.h - Abstraction for storing information -*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // MipsOptionRecord - Abstraction for storing arbitrary information in
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11 // ELF files. Arbitrary information (e.g. register usage) can be stored in Mips
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12 // specific ELF sections like .Mips.options. Specific records should subclass
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13 // MipsOptionRecord and provide an implementation to EmitMipsOptionRecord which
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14 // basically just dumps the information into an ELF section. More information
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15 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
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16 // specification.
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17 //
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18 //===----------------------------------------------------------------------===//
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19
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20 #ifndef LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
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21 #define LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
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22
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23 #include "MCTargetDesc/MipsMCTargetDesc.h"
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24 #include "llvm/MC/MCContext.h"
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25 #include "llvm/MC/MCRegisterInfo.h"
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26 #include <cstdint>
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27
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28 namespace llvm {
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29
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30 class MipsELFStreamer;
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31
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32 class MipsOptionRecord {
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33 public:
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34 virtual ~MipsOptionRecord() = default;
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35
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36 virtual void EmitMipsOptionRecord() = 0;
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37 };
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38
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39 class MipsRegInfoRecord : public MipsOptionRecord {
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40 public:
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41 MipsRegInfoRecord(MipsELFStreamer *S, MCContext &Context)
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42 : Streamer(S), Context(Context) {
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43 ri_gprmask = 0;
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44 ri_cprmask[0] = ri_cprmask[1] = ri_cprmask[2] = ri_cprmask[3] = 0;
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45 ri_gp_value = 0;
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46
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47 const MCRegisterInfo *TRI = Context.getRegisterInfo();
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48 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
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49 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
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50 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
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51 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
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52 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
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53 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
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54 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID));
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55 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
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56 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
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57 }
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59 ~MipsRegInfoRecord() override = default;
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61 void EmitMipsOptionRecord() override;
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62 void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo);
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63
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64 private:
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65 MipsELFStreamer *Streamer;
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66 MCContext &Context;
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67 const MCRegisterClass *GPR32RegClass;
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68 const MCRegisterClass *GPR64RegClass;
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69 const MCRegisterClass *FGR32RegClass;
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70 const MCRegisterClass *FGR64RegClass;
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71 const MCRegisterClass *AFGR64RegClass;
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72 const MCRegisterClass *MSA128BRegClass;
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73 const MCRegisterClass *COP0RegClass;
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74 const MCRegisterClass *COP2RegClass;
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75 const MCRegisterClass *COP3RegClass;
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76 uint32_t ri_gprmask;
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77 uint32_t ri_cprmask[4];
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78 int64_t ri_gp_value;
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79 };
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81 } // end namespace llvm
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83 #endif // LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H