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annotate lib/Target/NVPTX/NVPTXPeephole.cpp @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children 3a76565eade5
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 //===-- NVPTXPeephole.cpp - NVPTX Peephole Optimiztions -------------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // In NVPTX, NVPTXFrameLowering will emit following instruction at the beginning
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11 // of a MachineFunction.
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12 //
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13 // mov %SPL, %depot
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14 // cvta.local %SP, %SPL
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15 //
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16 // Because Frame Index is a generic address and alloca can only return generic
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17 // pointer, without this pass the instructions producing alloca'ed address will
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18 // be based on %SP. NVPTXLowerAlloca tends to help replace store and load on
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19 // this address with their .local versions, but this may introduce a lot of
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20 // cvta.to.local instructions. Performance can be improved if we avoid casting
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21 // address back and forth and directly calculate local address based on %SPL.
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22 // This peephole pass optimizes these cases, for example
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23 //
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24 // It will transform the following pattern
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25 // %vreg0<def> = LEA_ADDRi64 %VRFrame, 4
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26 // %vreg1<def> = cvta_to_local_yes_64 %vreg0
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27 //
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28 // into
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29 // %vreg1<def> = LEA_ADDRi64 %VRFrameLocal, 4
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30 //
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31 // %VRFrameLocal is the virtual register name of %SPL
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32 //
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33 //===----------------------------------------------------------------------===//
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34
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35 #include "NVPTX.h"
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36 #include "llvm/CodeGen/MachineFunctionPass.h"
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37 #include "llvm/CodeGen/MachineInstrBuilder.h"
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38 #include "llvm/CodeGen/MachineRegisterInfo.h"
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39 #include "llvm/Target/TargetInstrInfo.h"
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40 #include "llvm/Target/TargetRegisterInfo.h"
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41
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42 using namespace llvm;
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43
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44 #define DEBUG_TYPE "nvptx-peephole"
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45
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46 namespace llvm {
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47 void initializeNVPTXPeepholePass(PassRegistry &);
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48 }
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49
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50 namespace {
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51 struct NVPTXPeephole : public MachineFunctionPass {
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52 public:
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53 static char ID;
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54 NVPTXPeephole() : MachineFunctionPass(ID) {
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55 initializeNVPTXPeepholePass(*PassRegistry::getPassRegistry());
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56 }
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57
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58 bool runOnMachineFunction(MachineFunction &MF) override;
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59
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60 StringRef getPassName() const override {
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61 return "NVPTX optimize redundant cvta.to.local instruction";
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62 }
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63
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64 void getAnalysisUsage(AnalysisUsage &AU) const override {
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65 MachineFunctionPass::getAnalysisUsage(AU);
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66 }
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67 };
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68 }
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69
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70 char NVPTXPeephole::ID = 0;
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71
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72 INITIALIZE_PASS(NVPTXPeephole, "nvptx-peephole", "NVPTX Peephole", false, false)
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73
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74 static bool isCVTAToLocalCombinationCandidate(MachineInstr &Root) {
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75 auto &MBB = *Root.getParent();
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76 auto &MF = *MBB.getParent();
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77 // Check current instruction is cvta.to.local
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78 if (Root.getOpcode() != NVPTX::cvta_to_local_yes_64 &&
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79 Root.getOpcode() != NVPTX::cvta_to_local_yes)
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80 return false;
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81
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82 auto &Op = Root.getOperand(1);
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83 const auto &MRI = MF.getRegInfo();
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84 MachineInstr *GenericAddrDef = nullptr;
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85 if (Op.isReg() && TargetRegisterInfo::isVirtualRegister(Op.getReg())) {
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86 GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg());
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87 }
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88
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89 // Check the register operand is uniquely defined by LEA_ADDRi instruction
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90 if (!GenericAddrDef || GenericAddrDef->getParent() != &MBB ||
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91 (GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi64 &&
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92 GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi)) {
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93 return false;
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94 }
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95
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96 // Check the LEA_ADDRi operand is Frame index
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97 auto &BaseAddrOp = GenericAddrDef->getOperand(1);
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98 if (BaseAddrOp.isReg() && BaseAddrOp.getReg() == NVPTX::VRFrame) {
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99 return true;
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100 }
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101
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102 return false;
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103 }
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104
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105 static void CombineCVTAToLocal(MachineInstr &Root) {
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106 auto &MBB = *Root.getParent();
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107 auto &MF = *MBB.getParent();
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108 const auto &MRI = MF.getRegInfo();
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109 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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110 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
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111
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112 MachineInstrBuilder MIB =
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113 BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()),
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114 Root.getOperand(0).getReg())
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115 .addReg(NVPTX::VRFrameLocal)
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116 .add(Prev.getOperand(2));
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117
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118 MBB.insert((MachineBasicBlock::iterator)&Root, MIB);
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119
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120 // Check if MRI has only one non dbg use, which is Root
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121 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
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122 Prev.eraseFromParentAndMarkDBGValuesForRemoval();
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123 }
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124 Root.eraseFromParentAndMarkDBGValuesForRemoval();
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125 }
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126
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127 bool NVPTXPeephole::runOnMachineFunction(MachineFunction &MF) {
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128 if (skipFunction(*MF.getFunction()))
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129 return false;
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130
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131 bool Changed = false;
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132 // Loop over all of the basic blocks.
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133 for (auto &MBB : MF) {
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134 // Traverse the basic block.
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135 auto BlockIter = MBB.begin();
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136
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137 while (BlockIter != MBB.end()) {
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138 auto &MI = *BlockIter++;
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139 if (isCVTAToLocalCombinationCandidate(MI)) {
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140 CombineCVTAToLocal(MI);
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141 Changed = true;
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142 }
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143 } // Instruction
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144 } // Basic Block
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145
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146 // Remove unnecessary %VRFrame = cvta.local %VRFrameLocal
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147 const auto &MRI = MF.getRegInfo();
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148 if (MRI.use_empty(NVPTX::VRFrame)) {
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149 if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) {
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150 MI->eraseFromParentAndMarkDBGValuesForRemoval();
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151 }
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152 }
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153
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154 return Changed;
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155 }
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156
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157 MachineFunctionPass *llvm::createNVPTXPeephole() { return new NVPTXPeephole(); }