0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
3 // The LLVM Compiler Infrastructure
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
4 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
5 // This file is distributed under the University of Illinois Open Source
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
6 // License. See LICENSE.TXT for details.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
7 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
8 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
9 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
10 // Top-level implementation for the NVPTX target.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
11 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
12 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
13
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
14 #include "NVPTXTargetMachine.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
15 #include "NVPTX.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
16 #include "NVPTXAllocaHoisting.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
17 #include "NVPTXLowerAggrCopies.h"
|
|
83
|
18 #include "NVPTXTargetObjectFile.h"
|
|
|
19 #include "NVPTXTargetTransformInfo.h"
|
|
121
|
20 #include "llvm/ADT/STLExtras.h"
|
|
|
21 #include "llvm/ADT/Triple.h"
|
|
|
22 #include "llvm/Analysis/TargetTransformInfo.h"
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
23 #include "llvm/CodeGen/Passes.h"
|
|
120
|
24 #include "llvm/CodeGen/TargetPassConfig.h"
|
|
83
|
25 #include "llvm/IR/LegacyPassManager.h"
|
|
121
|
26 #include "llvm/Pass.h"
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
27 #include "llvm/Support/CommandLine.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
28 #include "llvm/Support/TargetRegistry.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
29 #include "llvm/Target/TargetMachine.h"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
30 #include "llvm/Target/TargetOptions.h"
|
|
121
|
31 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
32 #include "llvm/Transforms/Scalar.h"
|
|
120
|
33 #include "llvm/Transforms/Scalar/GVN.h"
|
|
|
34 #include "llvm/Transforms/Vectorize.h"
|
|
121
|
35 #include <cassert>
|
|
|
36 #include <string>
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
37
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
38 using namespace llvm;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
39
|
|
120
|
40 // LSV is still relatively new; this switch lets us turn it off in case we
|
|
|
41 // encounter (or suspect) a bug.
|
|
|
42 static cl::opt<bool>
|
|
|
43 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
|
|
|
44 cl::desc("Disable load/store vectorizer"),
|
|
|
45 cl::init(false), cl::Hidden);
|
|
|
46
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
47 namespace llvm {
|
|
121
|
48
|
|
120
|
49 void initializeNVVMIntrRangePass(PassRegistry&);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
50 void initializeNVVMReflectPass(PassRegistry&);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
51 void initializeGenericToNVVMPass(PassRegistry&);
|
|
95
|
52 void initializeNVPTXAllocaHoistingPass(PassRegistry &);
|
|
77
|
53 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
|
|
95
|
54 void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
|
|
120
|
55 void initializeNVPTXLowerArgsPass(PassRegistry &);
|
|
95
|
56 void initializeNVPTXLowerAllocaPass(PassRegistry &);
|
|
121
|
57
|
|
|
58 } // end namespace llvm
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
59
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
60 extern "C" void LLVMInitializeNVPTXTarget() {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
61 // Register the target.
|
|
120
|
62 RegisterTargetMachine<NVPTXTargetMachine32> X(getTheNVPTXTarget32());
|
|
|
63 RegisterTargetMachine<NVPTXTargetMachine64> Y(getTheNVPTXTarget64());
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
64
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
65 // FIXME: This pass is really intended to be invoked during IR optimization,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
66 // but it's very NVPTX-specific.
|
|
95
|
67 PassRegistry &PR = *PassRegistry::getPassRegistry();
|
|
|
68 initializeNVVMReflectPass(PR);
|
|
120
|
69 initializeNVVMIntrRangePass(PR);
|
|
95
|
70 initializeGenericToNVVMPass(PR);
|
|
|
71 initializeNVPTXAllocaHoistingPass(PR);
|
|
|
72 initializeNVPTXAssignValidGlobalNamesPass(PR);
|
|
120
|
73 initializeNVPTXLowerArgsPass(PR);
|
|
95
|
74 initializeNVPTXLowerAllocaPass(PR);
|
|
|
75 initializeNVPTXLowerAggrCopiesPass(PR);
|
|
83
|
76 }
|
|
|
77
|
|
|
78 static std::string computeDataLayout(bool is64Bit) {
|
|
|
79 std::string Ret = "e";
|
|
|
80
|
|
|
81 if (!is64Bit)
|
|
|
82 Ret += "-p:32:32";
|
|
|
83
|
|
121
|
84 Ret += "-i64:64-i128:128-v16:16-v32:32-n16:32:64";
|
|
83
|
85
|
|
|
86 return Ret;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
87 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
88
|
|
121
|
89 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
|
|
|
90 if (CM)
|
|
|
91 return *CM;
|
|
|
92 return CodeModel::Small;
|
|
|
93 }
|
|
|
94
|
|
95
|
95 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
|
|
77
|
96 StringRef CPU, StringRef FS,
|
|
|
97 const TargetOptions &Options,
|
|
120
|
98 Optional<Reloc::Model> RM,
|
|
121
|
99 Optional<CodeModel::Model> CM,
|
|
77
|
100 CodeGenOpt::Level OL, bool is64bit)
|
|
120
|
101 // The pic relocation model is used regardless of what the client has
|
|
|
102 // specified, as it is the only relocation model currently supported.
|
|
|
103 : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options,
|
|
121
|
104 Reloc::PIC_, getEffectiveCodeModel(CM), OL),
|
|
|
105 is64bit(is64bit), TLOF(llvm::make_unique<NVPTXTargetObjectFile>()),
|
|
95
|
106 Subtarget(TT, CPU, FS, *this) {
|
|
|
107 if (TT.getOS() == Triple::NVCL)
|
|
|
108 drvInterface = NVPTX::NVCL;
|
|
|
109 else
|
|
|
110 drvInterface = NVPTX::CUDA;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
111 initAsmInfo();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
112 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
113
|
|
121
|
114 NVPTXTargetMachine::~NVPTXTargetMachine() = default;
|
|
83
|
115
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
116 void NVPTXTargetMachine32::anchor() {}
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
117
|
|
95
|
118 NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
|
|
|
119 StringRef CPU, StringRef FS,
|
|
|
120 const TargetOptions &Options,
|
|
120
|
121 Optional<Reloc::Model> RM,
|
|
121
|
122 Optional<CodeModel::Model> CM,
|
|
|
123 CodeGenOpt::Level OL, bool JIT)
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
124 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
125
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
126 void NVPTXTargetMachine64::anchor() {}
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
127
|
|
95
|
128 NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
|
|
|
129 StringRef CPU, StringRef FS,
|
|
|
130 const TargetOptions &Options,
|
|
120
|
131 Optional<Reloc::Model> RM,
|
|
121
|
132 Optional<CodeModel::Model> CM,
|
|
|
133 CodeGenOpt::Level OL, bool JIT)
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
134 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
135
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
136 namespace {
|
|
121
|
137
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
138 class NVPTXPassConfig : public TargetPassConfig {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
139 public:
|
|
121
|
140 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
141 : TargetPassConfig(TM, PM) {}
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
142
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
143 NVPTXTargetMachine &getNVPTXTargetMachine() const {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
144 return getTM<NVPTXTargetMachine>();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
145 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
146
|
|
77
|
147 void addIRPasses() override;
|
|
|
148 bool addInstSelector() override;
|
|
83
|
149 void addPostRegAlloc() override;
|
|
77
|
150 void addMachineSSAOptimization() override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
151
|
|
77
|
152 FunctionPass *createTargetRegisterAllocator(bool) override;
|
|
|
153 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
|
|
|
154 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
|
|
95
|
155
|
|
|
156 private:
|
|
120
|
157 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
|
|
|
158 // function is only called in opt mode.
|
|
95
|
159 void addEarlyCSEOrGVNPass();
|
|
120
|
160
|
|
|
161 // Add passes that propagate special memory spaces.
|
|
|
162 void addAddressSpaceInferencePasses();
|
|
|
163
|
|
|
164 // Add passes that perform straight-line scalar optimizations.
|
|
|
165 void addStraightLineScalarOptimizationPasses();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
166 };
|
|
121
|
167
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
168 } // end anonymous namespace
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
169
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
170 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
|
|
121
|
171 return new NVPTXPassConfig(*this, PM);
|
|
120
|
172 }
|
|
|
173
|
|
121
|
174 void NVPTXTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
|
|
|
175 Builder.addExtension(
|
|
|
176 PassManagerBuilder::EP_EarlyAsPossible,
|
|
|
177 [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
|
|
|
178 PM.add(createNVVMReflectPass());
|
|
|
179 PM.add(createNVVMIntrRangePass(Subtarget.getSmVersion()));
|
|
|
180 });
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
181 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
182
|
|
83
|
183 TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
|
|
95
|
184 return TargetIRAnalysis([this](const Function &F) {
|
|
|
185 return TargetTransformInfo(NVPTXTTIImpl(this, F));
|
|
|
186 });
|
|
|
187 }
|
|
|
188
|
|
|
189 void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
|
|
|
190 if (getOptLevel() == CodeGenOpt::Aggressive)
|
|
|
191 addPass(createGVNPass());
|
|
|
192 else
|
|
|
193 addPass(createEarlyCSEPass());
|
|
83
|
194 }
|
|
|
195
|
|
120
|
196 void NVPTXPassConfig::addAddressSpaceInferencePasses() {
|
|
|
197 // NVPTXLowerArgs emits alloca for byval parameters which can often
|
|
95
|
198 // be eliminated by SROA.
|
|
|
199 addPass(createSROAPass());
|
|
|
200 addPass(createNVPTXLowerAllocaPass());
|
|
121
|
201 addPass(createInferAddressSpacesPass());
|
|
120
|
202 }
|
|
95
|
203
|
|
120
|
204 void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
|
|
77
|
205 addPass(createSeparateConstOffsetFromGEPPass());
|
|
95
|
206 addPass(createSpeculativeExecutionPass());
|
|
|
207 // ReassociateGEPs exposes more opportunites for SLSR. See
|
|
|
208 // the example in reassociate-geps-and-slsr.ll.
|
|
|
209 addPass(createStraightLineStrengthReducePass());
|
|
|
210 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
|
|
|
211 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
|
|
|
212 // for some of our benchmarks.
|
|
|
213 addEarlyCSEOrGVNPass();
|
|
|
214 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
|
|
|
215 addPass(createNaryReassociatePass());
|
|
|
216 // NaryReassociate on GEPs creates redundant common expressions, so run
|
|
|
217 // EarlyCSE after it.
|
|
|
218 addPass(createEarlyCSEPass());
|
|
120
|
219 }
|
|
|
220
|
|
|
221 void NVPTXPassConfig::addIRPasses() {
|
|
|
222 // The following passes are known to not play well with virtual regs hanging
|
|
|
223 // around after register allocation (which in our case, is *all* registers).
|
|
|
224 // We explicitly disable them here. We do, however, need some functionality
|
|
|
225 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
|
|
|
226 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
|
|
|
227 disablePass(&PrologEpilogCodeInserterID);
|
|
|
228 disablePass(&MachineCopyPropagationID);
|
|
|
229 disablePass(&TailDuplicateID);
|
|
|
230 disablePass(&StackMapLivenessID);
|
|
|
231 disablePass(&LiveDebugValuesID);
|
|
|
232 disablePass(&PostRASchedulerID);
|
|
|
233 disablePass(&FuncletLayoutID);
|
|
|
234 disablePass(&PatchableFunctionID);
|
|
|
235
|
|
|
236 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
|
|
|
237 // it here does nothing. But since we need it for correctness when lowering
|
|
|
238 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
|
|
|
239 // call addEarlyAsPossiblePasses.
|
|
|
240 addPass(createNVVMReflectPass());
|
|
|
241
|
|
|
242 if (getOptLevel() != CodeGenOpt::None)
|
|
|
243 addPass(createNVPTXImageOptimizerPass());
|
|
|
244 addPass(createNVPTXAssignValidGlobalNamesPass());
|
|
|
245 addPass(createGenericToNVVMPass());
|
|
|
246
|
|
|
247 // NVPTXLowerArgs is required for correctness and should be run right
|
|
|
248 // before the address space inference passes.
|
|
|
249 addPass(createNVPTXLowerArgsPass(&getNVPTXTargetMachine()));
|
|
|
250 if (getOptLevel() != CodeGenOpt::None) {
|
|
|
251 addAddressSpaceInferencePasses();
|
|
|
252 if (!DisableLoadStoreVectorizer)
|
|
|
253 addPass(createLoadStoreVectorizerPass());
|
|
|
254 addStraightLineScalarOptimizationPasses();
|
|
|
255 }
|
|
95
|
256
|
|
|
257 // === LSR and other generic IR passes ===
|
|
|
258 TargetPassConfig::addIRPasses();
|
|
|
259 // EarlyCSE is not always strong enough to clean up what LSR produces. For
|
|
|
260 // example, GVN can combine
|
|
77
|
261 //
|
|
95
|
262 // %0 = add %a, %b
|
|
|
263 // %1 = add %b, %a
|
|
|
264 //
|
|
|
265 // and
|
|
77
|
266 //
|
|
95
|
267 // %0 = shl nsw %a, 2
|
|
|
268 // %1 = shl %a, 2
|
|
|
269 //
|
|
|
270 // but EarlyCSE can do neither of them.
|
|
120
|
271 if (getOptLevel() != CodeGenOpt::None)
|
|
|
272 addEarlyCSEOrGVNPass();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
273 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
274
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
275 bool NVPTXPassConfig::addInstSelector() {
|
|
95
|
276 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
|
|
77
|
277
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
278 addPass(createLowerAggrCopies());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
279 addPass(createAllocaHoisting());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
280 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
|
|
77
|
281
|
|
|
282 if (!ST.hasImageHandles())
|
|
|
283 addPass(createNVPTXReplaceImageHandlesPass());
|
|
|
284
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
285 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
286 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
287
|
|
83
|
288 void NVPTXPassConfig::addPostRegAlloc() {
|
|
|
289 addPass(createNVPTXPrologEpilogPass(), false);
|
|
120
|
290 if (getOptLevel() != CodeGenOpt::None) {
|
|
|
291 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
|
|
|
292 // index with VRFrame register. NVPTXPeephole need to be run after that and
|
|
|
293 // will replace VRFrame with VRFrameLocal when possible.
|
|
|
294 addPass(createNVPTXPeephole());
|
|
|
295 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
296 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
297
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
298 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
|
|
77
|
299 return nullptr; // No reg alloc
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
300 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
301
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
302 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
303 assert(!RegAllocPass && "NVPTX uses no regalloc!");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
304 addPass(&PHIEliminationID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
305 addPass(&TwoAddressInstructionPassID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
306 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
307
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
308 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
309 assert(!RegAllocPass && "NVPTX uses no regalloc!");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
310
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
311 addPass(&ProcessImplicitDefsID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
312 addPass(&LiveVariablesID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
313 addPass(&MachineLoopInfoID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
314 addPass(&PHIEliminationID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
315
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
316 addPass(&TwoAddressInstructionPassID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
317 addPass(&RegisterCoalescerID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
318
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
319 // PreRA instruction scheduling.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
320 if (addPass(&MachineSchedulerID))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
321 printAndVerify("After Machine Scheduling");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
322
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
323
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
324 addPass(&StackSlotColoringID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
325
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
326 // FIXME: Needs physical registers
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
327 //addPass(&PostRAMachineLICMID);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
328
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
329 printAndVerify("After StackSlotColoring");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
330 }
|
|
77
|
331
|
|
|
332 void NVPTXPassConfig::addMachineSSAOptimization() {
|
|
|
333 // Pre-ra tail duplication.
|
|
|
334 if (addPass(&EarlyTailDuplicateID))
|
|
|
335 printAndVerify("After Pre-RegAlloc TailDuplicate");
|
|
|
336
|
|
|
337 // Optimize PHIs before DCE: removing dead PHI cycles may make more
|
|
|
338 // instructions dead.
|
|
|
339 addPass(&OptimizePHIsID);
|
|
|
340
|
|
|
341 // This pass merges large allocas. StackSlotColoring is a different pass
|
|
|
342 // which merges spill slots.
|
|
|
343 addPass(&StackColoringID);
|
|
|
344
|
|
|
345 // If the target requests it, assign local variables to stack slots relative
|
|
|
346 // to one another and simplify frame index references where possible.
|
|
|
347 addPass(&LocalStackSlotAllocationID);
|
|
|
348
|
|
|
349 // With optimization, dead code should already be eliminated. However
|
|
|
350 // there is one known exception: lowered code for arguments that are only
|
|
|
351 // used by tail calls, where the tail calls reuse the incoming stack
|
|
|
352 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
|
|
|
353 addPass(&DeadMachineInstructionElimID);
|
|
|
354 printAndVerify("After codegen DCE pass");
|
|
|
355
|
|
|
356 // Allow targets to insert passes that improve instruction level parallelism,
|
|
|
357 // like if-conversion. Such passes will typically need dominator trees and
|
|
|
358 // loop info, just like LICM and CSE below.
|
|
|
359 if (addILPOpts())
|
|
|
360 printAndVerify("After ILP optimizations");
|
|
|
361
|
|
|
362 addPass(&MachineLICMID);
|
|
|
363 addPass(&MachineCSEID);
|
|
|
364
|
|
|
365 addPass(&MachineSinkingID);
|
|
|
366 printAndVerify("After Machine LICM, CSE and Sinking passes");
|
|
|
367
|
|
|
368 addPass(&PeepholeOptimizerID);
|
|
|
369 printAndVerify("After codegen peephole optimization pass");
|
|
|
370 }
|
