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1 //==- SystemZInstrDFP.td - Floating-point SystemZ instructions -*- tblgen-*-==//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // The instructions in this file implement SystemZ decimal floating-point
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11 // arithmetic. These instructions are inot currently used for code generation,
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12 // are provided for use with the assembler and disassembler only. If LLVM
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13 // ever supports decimal floating-point types (_Decimal64 etc.), they can
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14 // also be used for code generation for those types.
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15 //
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16 //===----------------------------------------------------------------------===//
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17
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18 //===----------------------------------------------------------------------===//
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19 // Move instructions
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20 //===----------------------------------------------------------------------===//
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21
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22 // Load and test.
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23 let Defs = [CC] in {
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24 def LTDTR : UnaryRRE<"ltdtr", 0xB3D6, null_frag, FP64, FP64>;
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25 def LTXTR : UnaryRRE<"ltxtr", 0xB3DE, null_frag, FP128, FP128>;
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26 }
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27
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28
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29 //===----------------------------------------------------------------------===//
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30 // Conversion instructions
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31 //===----------------------------------------------------------------------===//
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32
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33 // Convert floating-point values to narrower representations. The destination
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34 // of LDXTR is a 128-bit value, but only the first register of the pair is used.
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35 def LEDTR : TernaryRRFe<"ledtr", 0xB3D5, FP32, FP64>;
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36 def LDXTR : TernaryRRFe<"ldxtr", 0xB3DD, FP128, FP128>;
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37
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38 // Extend floating-point values to wider representations.
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39 def LDETR : BinaryRRFd<"ldetr", 0xB3D4, FP64, FP32>;
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40 def LXDTR : BinaryRRFd<"lxdtr", 0xB3DC, FP128, FP64>;
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41
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42 // Convert a signed integer value to a floating-point one.
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43 def CDGTR : UnaryRRE<"cdgtr", 0xB3F1, null_frag, FP64, GR64>;
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44 def CXGTR : UnaryRRE<"cxgtr", 0xB3F9, null_frag, FP128, GR64>;
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45 let Predicates = [FeatureFPExtension] in {
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46 def CDGTRA : TernaryRRFe<"cdgtra", 0xB3F1, FP64, GR64>;
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47 def CXGTRA : TernaryRRFe<"cxgtra", 0xB3F9, FP128, GR64>;
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48 def CDFTR : TernaryRRFe<"cdftr", 0xB951, FP64, GR32>;
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49 def CXFTR : TernaryRRFe<"cxftr", 0xB959, FP128, GR32>;
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50 }
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51
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52 // Convert an unsigned integer value to a floating-point one.
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53 let Predicates = [FeatureFPExtension] in {
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54 def CDLGTR : TernaryRRFe<"cdlgtr", 0xB952, FP64, GR64>;
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55 def CXLGTR : TernaryRRFe<"cxlgtr", 0xB95A, FP128, GR64>;
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56 def CDLFTR : TernaryRRFe<"cdlftr", 0xB953, FP64, GR32>;
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57 def CXLFTR : TernaryRRFe<"cxlftr", 0xB95B, FP128, GR32>;
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58 }
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59
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60 // Convert a floating-point value to a signed integer value.
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61 let Defs = [CC] in {
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62 def CGDTR : BinaryRRFe<"cgdtr", 0xB3E1, GR64, FP64>;
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63 def CGXTR : BinaryRRFe<"cgxtr", 0xB3E9, GR64, FP128>;
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64 let Predicates = [FeatureFPExtension] in {
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65 def CGDTRA : TernaryRRFe<"cgdtra", 0xB3E1, GR64, FP64>;
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66 def CGXTRA : TernaryRRFe<"cgxtra", 0xB3E9, GR64, FP128>;
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67 def CFDTR : TernaryRRFe<"cfdtr", 0xB941, GR32, FP64>;
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68 def CFXTR : TernaryRRFe<"cfxtr", 0xB949, GR32, FP128>;
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69 }
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70 }
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71
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72 // Convert a floating-point value to an unsigned integer value.
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73 let Defs = [CC] in {
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74 let Predicates = [FeatureFPExtension] in {
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75 def CLGDTR : TernaryRRFe<"clgdtr", 0xB942, GR64, FP64>;
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76 def CLGXTR : TernaryRRFe<"clgxtr", 0xB94A, GR64, FP128>;
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77 def CLFDTR : TernaryRRFe<"clfdtr", 0xB943, GR32, FP64>;
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78 def CLFXTR : TernaryRRFe<"clfxtr", 0xB94B, GR32, FP128>;
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79 }
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80 }
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81
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82 // Convert a packed value to a floating-point one.
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83 def CDSTR : UnaryRRE<"cdstr", 0xB3F3, null_frag, FP64, GR64>;
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84 def CXSTR : UnaryRRE<"cxstr", 0xB3FB, null_frag, FP128, GR128>;
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85 def CDUTR : UnaryRRE<"cdutr", 0xB3F2, null_frag, FP64, GR64>;
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86 def CXUTR : UnaryRRE<"cxutr", 0xB3FA, null_frag, FP128, GR128>;
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87
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88 // Convert a floating-point value to a packed value.
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89 def CSDTR : BinaryRRFd<"csdtr", 0xB3E3, GR64, FP64>;
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90 def CSXTR : BinaryRRFd<"csxtr", 0xB3EB, GR128, FP128>;
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91 def CUDTR : UnaryRRE<"cudtr", 0xB3E2, null_frag, GR64, FP64>;
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92 def CUXTR : UnaryRRE<"cuxtr", 0xB3EA, null_frag, GR128, FP128>;
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93
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94 // Convert from/to memory values in the zoned format.
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95 let Predicates = [FeatureDFPZonedConversion] in {
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96 def CDZT : BinaryRSL<"cdzt", 0xEDAA, FP64>;
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97 def CXZT : BinaryRSL<"cxzt", 0xEDAB, FP128>;
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98 def CZDT : StoreBinaryRSL<"czdt", 0xEDA8, FP64>;
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99 def CZXT : StoreBinaryRSL<"czxt", 0xEDA9, FP128>;
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100 }
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101
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102 // Convert from/to memory values in the packed format.
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103 let Predicates = [FeatureDFPPackedConversion] in {
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104 def CDPT : BinaryRSL<"cdpt", 0xEDAE, FP64>;
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105 def CXPT : BinaryRSL<"cxpt", 0xEDAF, FP128>;
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106 def CPDT : StoreBinaryRSL<"cpdt", 0xEDAC, FP64>;
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107 def CPXT : StoreBinaryRSL<"cpxt", 0xEDAD, FP128>;
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108 }
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109
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110 // Perform floating-point operation.
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111 let Defs = [CC, R1L, F0Q], Uses = [R0L, F4Q] in
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112 def PFPO : SideEffectInherentE<"pfpo", 0x010A>;
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113
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114
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115 //===----------------------------------------------------------------------===//
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116 // Unary arithmetic
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117 //===----------------------------------------------------------------------===//
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118
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119 // Round to an integer, with the second operand (M3) specifying the rounding
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120 // mode. M4 can be set to 4 to suppress detection of inexact conditions.
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121 def FIDTR : TernaryRRFe<"fidtr", 0xB3D7, FP64, FP64>;
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122 def FIXTR : TernaryRRFe<"fixtr", 0xB3DF, FP128, FP128>;
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123
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124 // Extract biased exponent.
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125 def EEDTR : UnaryRRE<"eedtr", 0xB3E5, null_frag, FP64, FP64>;
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126 def EEXTR : UnaryRRE<"eextr", 0xB3ED, null_frag, FP128, FP128>;
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127
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128 // Extract significance.
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129 def ESDTR : UnaryRRE<"esdtr", 0xB3E7, null_frag, FP64, FP64>;
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130 def ESXTR : UnaryRRE<"esxtr", 0xB3EF, null_frag, FP128, FP128>;
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131
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132
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133 //===----------------------------------------------------------------------===//
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134 // Binary arithmetic
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135 //===----------------------------------------------------------------------===//
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136
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137 // Addition.
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138 let Defs = [CC] in {
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139 let isCommutable = 1 in {
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140 def ADTR : BinaryRRFa<"adtr", 0xB3D2, null_frag, FP64, FP64, FP64>;
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141 def AXTR : BinaryRRFa<"axtr", 0xB3DA, null_frag, FP128, FP128, FP128>;
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142 }
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143 let Predicates = [FeatureFPExtension] in {
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144 def ADTRA : TernaryRRFa<"adtra", 0xB3D2, FP64, FP64, FP64>;
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145 def AXTRA : TernaryRRFa<"axtra", 0xB3DA, FP128, FP128, FP128>;
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146 }
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147 }
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148
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149 // Subtraction.
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150 let Defs = [CC] in {
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151 def SDTR : BinaryRRFa<"sdtr", 0xB3D3, null_frag, FP64, FP64, FP64>;
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152 def SXTR : BinaryRRFa<"sxtr", 0xB3DB, null_frag, FP128, FP128, FP128>;
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153 let Predicates = [FeatureFPExtension] in {
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154 def SDTRA : TernaryRRFa<"sdtra", 0xB3D3, FP64, FP64, FP64>;
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155 def SXTRA : TernaryRRFa<"sxtra", 0xB3DB, FP128, FP128, FP128>;
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156 }
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157 }
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158
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159 // Multiplication.
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160 let isCommutable = 1 in {
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161 def MDTR : BinaryRRFa<"mdtr", 0xB3D0, null_frag, FP64, FP64, FP64>;
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162 def MXTR : BinaryRRFa<"mxtr", 0xB3D8, null_frag, FP128, FP128, FP128>;
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163 }
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164 let Predicates = [FeatureFPExtension] in {
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165 def MDTRA : TernaryRRFa<"mdtra", 0xB3D0, FP64, FP64, FP64>;
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166 def MXTRA : TernaryRRFa<"mxtra", 0xB3D8, FP128, FP128, FP128>;
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167 }
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168
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169 // Division.
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170 def DDTR : BinaryRRFa<"ddtr", 0xB3D1, null_frag, FP64, FP64, FP64>;
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171 def DXTR : BinaryRRFa<"dxtr", 0xB3D9, null_frag, FP128, FP128, FP128>;
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172 let Predicates = [FeatureFPExtension] in {
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173 def DDTRA : TernaryRRFa<"ddtra", 0xB3D1, FP64, FP64, FP64>;
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174 def DXTRA : TernaryRRFa<"dxtra", 0xB3D9, FP128, FP128, FP128>;
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175 }
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176
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177 // Quantize.
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178 def QADTR : TernaryRRFb<"qadtr", 0xB3F5, FP64, FP64, FP64>;
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179 def QAXTR : TernaryRRFb<"qaxtr", 0xB3FD, FP128, FP128, FP128>;
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180
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181 // Reround.
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182 def RRDTR : TernaryRRFb<"rrdtr", 0xB3F7, FP64, FP64, FP64>;
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183 def RRXTR : TernaryRRFb<"rrxtr", 0xB3FF, FP128, FP128, FP128>;
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184
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185 // Shift significand left/right.
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186 def SLDT : BinaryRXF<"sldt", 0xED40, null_frag, FP64, FP64, null_frag, 0>;
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187 def SLXT : BinaryRXF<"slxt", 0xED48, null_frag, FP128, FP128, null_frag, 0>;
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188 def SRDT : BinaryRXF<"srdt", 0xED41, null_frag, FP64, FP64, null_frag, 0>;
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189 def SRXT : BinaryRXF<"srxt", 0xED49, null_frag, FP128, FP128, null_frag, 0>;
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190
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191 // Insert biased exponent.
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192 def IEDTR : BinaryRRFb<"iedtr", 0xB3F6, null_frag, FP64, FP64, FP64>;
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193 def IEXTR : BinaryRRFb<"iextr", 0xB3FE, null_frag, FP128, FP128, FP128>;
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194
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195
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196 //===----------------------------------------------------------------------===//
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197 // Comparisons
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198 //===----------------------------------------------------------------------===//
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199
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200 // Compare.
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201 let Defs = [CC] in {
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202 def CDTR : CompareRRE<"cdtr", 0xB3E4, null_frag, FP64, FP64>;
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203 def CXTR : CompareRRE<"cxtr", 0xB3EC, null_frag, FP128, FP128>;
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204 }
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205
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206 // Compare and signal.
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207 let Defs = [CC] in {
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208 def KDTR : CompareRRE<"kdtr", 0xB3E0, null_frag, FP64, FP64>;
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209 def KXTR : CompareRRE<"kxtr", 0xB3E8, null_frag, FP128, FP128>;
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210 }
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211
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212 // Compare biased exponent.
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213 let Defs = [CC] in {
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214 def CEDTR : CompareRRE<"cedtr", 0xB3F4, null_frag, FP64, FP64>;
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215 def CEXTR : CompareRRE<"cextr", 0xB3FC, null_frag, FP128, FP128>;
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216 }
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217
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218 // Test Data Class.
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219 let Defs = [CC] in {
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220 def TDCET : TestRXE<"tdcet", 0xED50, null_frag, FP32>;
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221 def TDCDT : TestRXE<"tdcdt", 0xED54, null_frag, FP64>;
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222 def TDCXT : TestRXE<"tdcxt", 0xED58, null_frag, FP128>;
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223 }
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224
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225 // Test Data Group.
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226 let Defs = [CC] in {
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227 def TDGET : TestRXE<"tdget", 0xED51, null_frag, FP32>;
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228 def TDGDT : TestRXE<"tdgdt", 0xED55, null_frag, FP64>;
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229 def TDGXT : TestRXE<"tdgxt", 0xED59, null_frag, FP128>;
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230 }
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231
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