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1 //===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 /// \file
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10 /// This file implements the targeting of the Machinelegalizer class for X86.
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11 /// \todo This should be generated by TableGen.
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "X86LegalizerInfo.h"
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15 #include "X86Subtarget.h"
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16 #include "X86TargetMachine.h"
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17 #include "llvm/CodeGen/ValueTypes.h"
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18 #include "llvm/IR/DerivedTypes.h"
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19 #include "llvm/IR/Type.h"
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20 #include "llvm/Target/TargetOpcodes.h"
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21
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22 using namespace llvm;
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23 using namespace TargetOpcode;
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24
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25 X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
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26 const X86TargetMachine &TM)
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27 : Subtarget(STI), TM(TM) {
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28
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29 setLegalizerInfo32bit();
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30 setLegalizerInfo64bit();
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31 setLegalizerInfoSSE1();
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32 setLegalizerInfoSSE2();
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33 setLegalizerInfoSSE41();
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34 setLegalizerInfoAVX();
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35 setLegalizerInfoAVX2();
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36 setLegalizerInfoAVX512();
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37 setLegalizerInfoAVX512DQ();
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38 setLegalizerInfoAVX512BW();
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39
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40 computeTables();
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41 }
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42
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43 void X86LegalizerInfo::setLegalizerInfo32bit() {
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44
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45 const LLT p0 = LLT::pointer(0, TM.getPointerSize() * 8);
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46 const LLT s1 = LLT::scalar(1);
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47 const LLT s8 = LLT::scalar(8);
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48 const LLT s16 = LLT::scalar(16);
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49 const LLT s32 = LLT::scalar(32);
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50 const LLT s64 = LLT::scalar(64);
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51
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52 for (auto Ty : {p0, s1, s8, s16, s32})
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53 setAction({G_IMPLICIT_DEF, Ty}, Legal);
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54
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55 for (auto Ty : {s8, s16, s32, p0})
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56 setAction({G_PHI, Ty}, Legal);
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57
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58 setAction({G_PHI, s1}, WidenScalar);
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59
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60 for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) {
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61 for (auto Ty : {s8, s16, s32})
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62 setAction({BinOp, Ty}, Legal);
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63
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64 setAction({BinOp, s1}, WidenScalar);
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65 }
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66
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67 for (unsigned Op : {G_UADDE}) {
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68 setAction({Op, s32}, Legal);
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69 setAction({Op, 1, s1}, Legal);
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70 }
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71
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72 for (unsigned MemOp : {G_LOAD, G_STORE}) {
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73 for (auto Ty : {s8, s16, s32, p0})
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74 setAction({MemOp, Ty}, Legal);
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75
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76 setAction({MemOp, s1}, WidenScalar);
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77 // And everything's fine in addrspace 0.
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78 setAction({MemOp, 1, p0}, Legal);
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79 }
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80
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81 // Pointer-handling
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82 setAction({G_FRAME_INDEX, p0}, Legal);
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83 setAction({G_GLOBAL_VALUE, p0}, Legal);
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84
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85 setAction({G_GEP, p0}, Legal);
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86 setAction({G_GEP, 1, s32}, Legal);
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87
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88 for (auto Ty : {s1, s8, s16})
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89 setAction({G_GEP, 1, Ty}, WidenScalar);
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90
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91 // Control-flow
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92 setAction({G_BRCOND, s1}, Legal);
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93
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94 // Constants
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95 for (auto Ty : {s8, s16, s32, p0})
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96 setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
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97
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98 setAction({TargetOpcode::G_CONSTANT, s1}, WidenScalar);
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99 setAction({TargetOpcode::G_CONSTANT, s64}, NarrowScalar);
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100
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101 // Extensions
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102 for (auto Ty : {s8, s16, s32}) {
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103 setAction({G_ZEXT, Ty}, Legal);
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104 setAction({G_SEXT, Ty}, Legal);
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105 setAction({G_ANYEXT, Ty}, Legal);
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106 }
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107
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108 for (auto Ty : {s1, s8, s16}) {
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109 setAction({G_ZEXT, 1, Ty}, Legal);
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110 setAction({G_SEXT, 1, Ty}, Legal);
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111 setAction({G_ANYEXT, 1, Ty}, Legal);
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112 }
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113
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114 // Comparison
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115 setAction({G_ICMP, s1}, Legal);
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116
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117 for (auto Ty : {s8, s16, s32, p0})
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118 setAction({G_ICMP, 1, Ty}, Legal);
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119 }
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120
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121 void X86LegalizerInfo::setLegalizerInfo64bit() {
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122
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123 if (!Subtarget.is64Bit())
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124 return;
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125
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126 const LLT s32 = LLT::scalar(32);
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127 const LLT s64 = LLT::scalar(64);
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128
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129 setAction({G_IMPLICIT_DEF, s64}, Legal);
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130
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131 setAction({G_PHI, s64}, Legal);
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132
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133 for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
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134 setAction({BinOp, s64}, Legal);
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135
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136 for (unsigned MemOp : {G_LOAD, G_STORE})
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137 setAction({MemOp, s64}, Legal);
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138
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139 // Pointer-handling
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140 setAction({G_GEP, 1, s64}, Legal);
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141
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142 // Constants
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143 setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
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144
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145 // Extensions
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146 for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
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147 setAction({extOp, s64}, Legal);
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148 setAction({extOp, 1, s32}, Legal);
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149 }
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150
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151 // Comparison
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152 setAction({G_ICMP, 1, s64}, Legal);
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153 }
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154
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155 void X86LegalizerInfo::setLegalizerInfoSSE1() {
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156 if (!Subtarget.hasSSE1())
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157 return;
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158
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159 const LLT s32 = LLT::scalar(32);
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160 const LLT v4s32 = LLT::vector(4, 32);
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161 const LLT v2s64 = LLT::vector(2, 64);
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162
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163 for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
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164 for (auto Ty : {s32, v4s32})
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165 setAction({BinOp, Ty}, Legal);
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166
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167 for (unsigned MemOp : {G_LOAD, G_STORE})
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168 for (auto Ty : {v4s32, v2s64})
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169 setAction({MemOp, Ty}, Legal);
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170
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171 // Constants
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172 setAction({TargetOpcode::G_FCONSTANT, s32}, Legal);
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173 }
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174
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175 void X86LegalizerInfo::setLegalizerInfoSSE2() {
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176 if (!Subtarget.hasSSE2())
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177 return;
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178
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179 const LLT s32 = LLT::scalar(32);
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180 const LLT s64 = LLT::scalar(64);
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181 const LLT v16s8 = LLT::vector(16, 8);
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182 const LLT v8s16 = LLT::vector(8, 16);
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183 const LLT v4s32 = LLT::vector(4, 32);
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184 const LLT v2s64 = LLT::vector(2, 64);
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185
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186 for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
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187 for (auto Ty : {s64, v2s64})
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188 setAction({BinOp, Ty}, Legal);
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189
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190 for (unsigned BinOp : {G_ADD, G_SUB})
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191 for (auto Ty : {v16s8, v8s16, v4s32, v2s64})
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192 setAction({BinOp, Ty}, Legal);
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193
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194 setAction({G_MUL, v8s16}, Legal);
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195
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196 setAction({G_FPEXT, s64}, Legal);
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197 setAction({G_FPEXT, 1, s32}, Legal);
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198
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199 // Constants
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200 setAction({TargetOpcode::G_FCONSTANT, s64}, Legal);
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201 }
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202
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203 void X86LegalizerInfo::setLegalizerInfoSSE41() {
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204 if (!Subtarget.hasSSE41())
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205 return;
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206
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207 const LLT v4s32 = LLT::vector(4, 32);
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208
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209 setAction({G_MUL, v4s32}, Legal);
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210 }
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211
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212 void X86LegalizerInfo::setLegalizerInfoAVX() {
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213 if (!Subtarget.hasAVX())
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214 return;
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215
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216 const LLT v16s8 = LLT::vector(16, 8);
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217 const LLT v8s16 = LLT::vector(8, 16);
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218 const LLT v4s32 = LLT::vector(4, 32);
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219 const LLT v2s64 = LLT::vector(2, 64);
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220
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221 const LLT v32s8 = LLT::vector(32, 8);
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222 const LLT v16s16 = LLT::vector(16, 16);
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223 const LLT v8s32 = LLT::vector(8, 32);
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224 const LLT v4s64 = LLT::vector(4, 64);
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225
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226 for (unsigned MemOp : {G_LOAD, G_STORE})
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227 for (auto Ty : {v8s32, v4s64})
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228 setAction({MemOp, Ty}, Legal);
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229
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230 for (auto Ty : {v32s8, v16s16, v8s32, v4s64}) {
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231 setAction({G_INSERT, Ty}, Legal);
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232 setAction({G_EXTRACT, 1, Ty}, Legal);
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233 }
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234 for (auto Ty : {v16s8, v8s16, v4s32, v2s64}) {
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235 setAction({G_INSERT, 1, Ty}, Legal);
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236 setAction({G_EXTRACT, Ty}, Legal);
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237 }
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238 }
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239
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240 void X86LegalizerInfo::setLegalizerInfoAVX2() {
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241 if (!Subtarget.hasAVX2())
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242 return;
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243
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244 const LLT v32s8 = LLT::vector(32, 8);
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245 const LLT v16s16 = LLT::vector(16, 16);
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246 const LLT v8s32 = LLT::vector(8, 32);
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247 const LLT v4s64 = LLT::vector(4, 64);
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248
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249 for (unsigned BinOp : {G_ADD, G_SUB})
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250 for (auto Ty : {v32s8, v16s16, v8s32, v4s64})
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251 setAction({BinOp, Ty}, Legal);
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252
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253 for (auto Ty : {v16s16, v8s32})
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254 setAction({G_MUL, Ty}, Legal);
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255 }
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256
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257 void X86LegalizerInfo::setLegalizerInfoAVX512() {
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258 if (!Subtarget.hasAVX512())
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259 return;
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260
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261 const LLT v16s8 = LLT::vector(16, 8);
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262 const LLT v8s16 = LLT::vector(8, 16);
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263 const LLT v4s32 = LLT::vector(4, 32);
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264 const LLT v2s64 = LLT::vector(2, 64);
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265
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266 const LLT v32s8 = LLT::vector(32, 8);
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267 const LLT v16s16 = LLT::vector(16, 16);
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268 const LLT v8s32 = LLT::vector(8, 32);
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269 const LLT v4s64 = LLT::vector(4, 64);
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270
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271 const LLT v64s8 = LLT::vector(64, 8);
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272 const LLT v32s16 = LLT::vector(32, 16);
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273 const LLT v16s32 = LLT::vector(16, 32);
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274 const LLT v8s64 = LLT::vector(8, 64);
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275
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276 for (unsigned BinOp : {G_ADD, G_SUB})
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277 for (auto Ty : {v16s32, v8s64})
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278 setAction({BinOp, Ty}, Legal);
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279
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280 setAction({G_MUL, v16s32}, Legal);
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281
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282 for (unsigned MemOp : {G_LOAD, G_STORE})
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283 for (auto Ty : {v16s32, v8s64})
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284 setAction({MemOp, Ty}, Legal);
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285
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286 for (auto Ty : {v64s8, v32s16, v16s32, v8s64}) {
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287 setAction({G_INSERT, Ty}, Legal);
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288 setAction({G_EXTRACT, 1, Ty}, Legal);
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289 }
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290 for (auto Ty : {v32s8, v16s16, v8s32, v4s64, v16s8, v8s16, v4s32, v2s64}) {
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291 setAction({G_INSERT, 1, Ty}, Legal);
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292 setAction({G_EXTRACT, Ty}, Legal);
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293 }
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294
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295 /************ VLX *******************/
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296 if (!Subtarget.hasVLX())
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297 return;
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298
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299 for (auto Ty : {v4s32, v8s32})
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300 setAction({G_MUL, Ty}, Legal);
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301 }
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302
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303 void X86LegalizerInfo::setLegalizerInfoAVX512DQ() {
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304 if (!(Subtarget.hasAVX512() && Subtarget.hasDQI()))
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305 return;
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306
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307 const LLT v8s64 = LLT::vector(8, 64);
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308
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309 setAction({G_MUL, v8s64}, Legal);
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310
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311 /************ VLX *******************/
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312 if (!Subtarget.hasVLX())
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313 return;
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314
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315 const LLT v2s64 = LLT::vector(2, 64);
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316 const LLT v4s64 = LLT::vector(4, 64);
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317
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318 for (auto Ty : {v2s64, v4s64})
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319 setAction({G_MUL, Ty}, Legal);
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320 }
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321
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322 void X86LegalizerInfo::setLegalizerInfoAVX512BW() {
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323 if (!(Subtarget.hasAVX512() && Subtarget.hasBWI()))
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324 return;
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325
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326 const LLT v64s8 = LLT::vector(64, 8);
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327 const LLT v32s16 = LLT::vector(32, 16);
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328
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329 for (unsigned BinOp : {G_ADD, G_SUB})
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330 for (auto Ty : {v64s8, v32s16})
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331 setAction({BinOp, Ty}, Legal);
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332
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333 setAction({G_MUL, v32s16}, Legal);
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334
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335 /************ VLX *******************/
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336 if (!Subtarget.hasVLX())
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337 return;
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338
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339 const LLT v8s16 = LLT::vector(8, 16);
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340 const LLT v16s16 = LLT::vector(16, 16);
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341
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342 for (auto Ty : {v8s16, v16s16})
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343 setAction({G_MUL, Ty}, Legal);
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344 }
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