Mercurial > hg > CbC > CbC_llvm

annotate test/CodeGen/AMDGPU/memory-legalizer-store.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents
children 3a76565eade5
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
121
803732b1fca8 LLVM 5.0
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1 ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s
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2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s
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3 ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s
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4 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s
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5
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6 declare i32 @llvm.amdgcn.workitem.id.x()
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7
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8 ; GCN-LABEL: {{^}}system_unordered
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9 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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10 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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11 define amdgpu_kernel void @system_unordered(
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12 i32 %in, i32 addrspace(4)* %out) {
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13 entry:
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14 store atomic i32 %in, i32 addrspace(4)* %out unordered, align 4
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15 ret void
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16 }
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17
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18 ; GCN-LABEL: {{^}}system_monotonic
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19 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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20 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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21 define amdgpu_kernel void @system_monotonic(
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22 i32 %in, i32 addrspace(4)* %out) {
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23 entry:
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24 store atomic i32 %in, i32 addrspace(4)* %out monotonic, align 4
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25 ret void
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26 }
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27
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28 ; GCN-LABEL: {{^}}system_release
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29 ; GCN: s_waitcnt vmcnt(0){{$}}
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30 ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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31 define amdgpu_kernel void @system_release(
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32 i32 %in, i32 addrspace(4)* %out) {
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33 entry:
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34 store atomic i32 %in, i32 addrspace(4)* %out release, align 4
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35 ret void
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36 }
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37
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38 ; GCN-LABEL: {{^}}system_seq_cst
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39 ; GCN: s_waitcnt vmcnt(0){{$}}
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40 ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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41 define amdgpu_kernel void @system_seq_cst(
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42 i32 %in, i32 addrspace(4)* %out) {
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43 entry:
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44 store atomic i32 %in, i32 addrspace(4)* %out seq_cst, align 4
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45 ret void
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46 }
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47
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48 ; GCN-LABEL: {{^}}singlethread_unordered
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49 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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50 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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51 define amdgpu_kernel void @singlethread_unordered(
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52 i32 %in, i32 addrspace(4)* %out) {
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53 entry:
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54 store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") unordered, align 4
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55 ret void
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56 }
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57
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58 ; GCN-LABEL: {{^}}singlethread_monotonic
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59 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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60 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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61 define amdgpu_kernel void @singlethread_monotonic(
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62 i32 %in, i32 addrspace(4)* %out) {
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63 entry:
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64 store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") monotonic, align 4
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65 ret void
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66 }
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67
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68 ; GCN-LABEL: {{^}}singlethread_release
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69 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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70 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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71 define amdgpu_kernel void @singlethread_release(
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72 i32 %in, i32 addrspace(4)* %out) {
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73 entry:
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74 store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") release, align 4
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75 ret void
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76 }
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77
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78 ; GCN-LABEL: {{^}}singlethread_seq_cst
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79 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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80 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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81 define amdgpu_kernel void @singlethread_seq_cst(
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82 i32 %in, i32 addrspace(4)* %out) {
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83 entry:
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84 store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") seq_cst, align 4
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85 ret void
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86 }
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87
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88 ; GCN-LABEL: {{^}}agent_unordered
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89 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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90 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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91 define amdgpu_kernel void @agent_unordered(
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92 i32 %in, i32 addrspace(4)* %out) {
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93 entry:
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94 store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") unordered, align 4
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95 ret void
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96 }
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97
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98 ; GCN-LABEL: {{^}}agent_monotonic
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99 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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100 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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101 define amdgpu_kernel void @agent_monotonic(
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102 i32 %in, i32 addrspace(4)* %out) {
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103 entry:
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104 store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") monotonic, align 4
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105 ret void
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106 }
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107
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108 ; GCN-LABEL: {{^}}agent_release
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109 ; GCN: s_waitcnt vmcnt(0){{$}}
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110 ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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111 define amdgpu_kernel void @agent_release(
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112 i32 %in, i32 addrspace(4)* %out) {
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113 entry:
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114 store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") release, align 4
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115 ret void
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116 }
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117
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118 ; GCN-LABEL: {{^}}agent_seq_cst
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119 ; GCN: s_waitcnt vmcnt(0){{$}}
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120 ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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121 define amdgpu_kernel void @agent_seq_cst(
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122 i32 %in, i32 addrspace(4)* %out) {
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123 entry:
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124 store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") seq_cst, align 4
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125 ret void
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126 }
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127
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128 ; GCN-LABEL: {{^}}workgroup_unordered
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129 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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130 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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131 define amdgpu_kernel void @workgroup_unordered(
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132 i32 %in, i32 addrspace(4)* %out) {
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133 entry:
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134 store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") unordered, align 4
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135 ret void
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136 }
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137
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138 ; GCN-LABEL: {{^}}workgroup_monotonic
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139 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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140 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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141 define amdgpu_kernel void @workgroup_monotonic(
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142 i32 %in, i32 addrspace(4)* %out) {
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143 entry:
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144 store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") monotonic, align 4
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145 ret void
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146 }
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147
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148 ; GCN-LABEL: {{^}}workgroup_release
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149 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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150 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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151 define amdgpu_kernel void @workgroup_release(
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152 i32 %in, i32 addrspace(4)* %out) {
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153 entry:
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154 store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") release, align 4
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155 ret void
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156 }
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157
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158 ; GCN-LABEL: {{^}}workgroup_seq_cst
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159 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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160 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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161 define amdgpu_kernel void @workgroup_seq_cst(
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162 i32 %in, i32 addrspace(4)* %out) {
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163 entry:
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164 store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") seq_cst, align 4
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165 ret void
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166 }
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167
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168 ; GCN-LABEL: {{^}}wavefront_unordered
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169 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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170 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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171 define amdgpu_kernel void @wavefront_unordered(
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172 i32 %in, i32 addrspace(4)* %out) {
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173 entry:
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174 store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") unordered, align 4
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175 ret void
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176 }
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177
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178 ; GCN-LABEL: {{^}}wavefront_monotonic
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179 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
180 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
181 define amdgpu_kernel void @wavefront_monotonic(
803732b1fca8 LLVM 5.0
kono
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diff changeset
182 i32 %in, i32 addrspace(4)* %out) {
803732b1fca8 LLVM 5.0
kono
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diff changeset
183 entry:
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
184 store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") monotonic, align 4
803732b1fca8 LLVM 5.0
kono
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diff changeset
185 ret void
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
186 }
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
187
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
188 ; GCN-LABEL: {{^}}wavefront_release
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
189 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
190 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
191 define amdgpu_kernel void @wavefront_release(
803732b1fca8 LLVM 5.0
kono
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diff changeset
192 i32 %in, i32 addrspace(4)* %out) {
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
193 entry:
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
194 store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") release, align 4
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
195 ret void
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
196 }
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
197
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
198 ; GCN-LABEL: {{^}}wavefront_seq_cst
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
199 ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
200 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
201 define amdgpu_kernel void @wavefront_seq_cst(
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
202 i32 %in, i32 addrspace(4)* %out) {
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
203 entry:
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
204 store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") seq_cst, align 4
803732b1fca8 LLVM 5.0
kono
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205 ret void
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
206 }
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
207
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
208 ; GCN-LABEL: {{^}}nontemporal_private_0
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
209 ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
210 define amdgpu_kernel void @nontemporal_private_0(
803732b1fca8 LLVM 5.0
kono
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diff changeset
211 i32 addrspace(4)* %in, i32* %out) {
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
212 entry:
803732b1fca8 LLVM 5.0
kono
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213 %val = load i32, i32 addrspace(4)* %in, align 4
803732b1fca8 LLVM 5.0
kono
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214 store i32 %val, i32* %out, !nontemporal !0
803732b1fca8 LLVM 5.0
kono
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diff changeset
215 ret void
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
216 }
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
217
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
218 ; GCN-LABEL: {{^}}nontemporal_private_1
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
219 ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
220 define amdgpu_kernel void @nontemporal_private_1(
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
221 i32 addrspace(4)* %in, i32* %out) {
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
222 entry:
803732b1fca8 LLVM 5.0
kono
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223 %tid = call i32 @llvm.amdgcn.workitem.id.x()
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
224 %val = load i32, i32 addrspace(4)* %in, align 4
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
225 %out.gep = getelementptr inbounds i32, i32* %out, i32 %tid
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
226 store i32 %val, i32* %out.gep, !nontemporal !0
803732b1fca8 LLVM 5.0
kono
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diff changeset
227 ret void
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
228 }
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
229
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
230 ; GCN-LABEL: {{^}}nontemporal_global_0
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
231 ; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
232 ; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
233 define amdgpu_kernel void @nontemporal_global_0(
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
234 i32 addrspace(4)* %in, i32 addrspace(1)* %out) {
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
235 entry:
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
236 %val = load i32, i32 addrspace(4)* %in, align 4
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
237 store i32 %val, i32 addrspace(1)* %out, !nontemporal !0
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
238 ret void
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
239 }
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
240
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
241 ; GCN-LABEL: {{^}}nontemporal_global_1
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
242 ; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
243 ; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
244 define amdgpu_kernel void @nontemporal_global_1(
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
245 i32 addrspace(4)* %in, i32 addrspace(1)* %out) {
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
246 entry:
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
247 %tid = call i32 @llvm.amdgcn.workitem.id.x()
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
248 %val = load i32, i32 addrspace(4)* %in, align 4
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
249 %out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
250 store i32 %val, i32 addrspace(1)* %out.gep, !nontemporal !0
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
251 ret void
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
252 }
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
253
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
254 ; GCN-LABEL: {{^}}nontemporal_local_0
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
255 ; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
256 define amdgpu_kernel void @nontemporal_local_0(
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
257 i32 addrspace(4)* %in, i32 addrspace(3)* %out) {
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
258 entry:
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
259 %val = load i32, i32 addrspace(4)* %in, align 4
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
260 store i32 %val, i32 addrspace(3)* %out, !nontemporal !0
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
261 ret void
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
262 }
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
263
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
264 ; GCN-LABEL: {{^}}nontemporal_local_1
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
265 ; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
266 define amdgpu_kernel void @nontemporal_local_1(
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
267 i32 addrspace(4)* %in, i32 addrspace(3)* %out) {
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
268 entry:
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
269 %tid = call i32 @llvm.amdgcn.workitem.id.x()
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
270 %val = load i32, i32 addrspace(4)* %in, align 4
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
271 %out.gep = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tid
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
272 store i32 %val, i32 addrspace(3)* %out.gep, !nontemporal !0
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
273 ret void
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
274 }
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
275
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
276 ; GCN-LABEL: {{^}}nontemporal_flat_0
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
277 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
278 define amdgpu_kernel void @nontemporal_flat_0(
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
279 i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
280 entry:
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
281 %val = load i32, i32 addrspace(4)* %in, align 4
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
282 store i32 %val, i32 addrspace(4)* %out, !nontemporal !0
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
283 ret void
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
284 }
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
285
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
286 ; GCN-LABEL: {{^}}nontemporal_flat_1
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
287 ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
288 define amdgpu_kernel void @nontemporal_flat_1(
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
289 i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
290 entry:
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
291 %tid = call i32 @llvm.amdgcn.workitem.id.x()
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
292 %val = load i32, i32 addrspace(4)* %in, align 4
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
293 %out.gep = getelementptr inbounds i32, i32 addrspace(4)* %out, i32 %tid
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
294 store i32 %val, i32 addrspace(4)* %out.gep, !nontemporal !0
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
295 ret void
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
296 }
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
297
803732b1fca8 LLVM 5.0
kono
parents:
diff changeset
298 !0 = !{i32 1}