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annotate test/CodeGen/AMDGPU/uint_to_fp.f64.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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3 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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4
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5 ; SI-LABEL: {{^}}v_uint_to_fp_i64_to_f64
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6 ; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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7 ; SI-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
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8 ; SI-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
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9 ; SI-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
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10 ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
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11 ; SI: buffer_store_dwordx2 [[RESULT]]
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12 define amdgpu_kernel void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) {
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13 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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14 %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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15 %val = load i64, i64 addrspace(1)* %gep, align 8
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16 %result = uitofp i64 %val to double
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17 store double %result, double addrspace(1)* %out
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18 ret void
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19 }
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21 ; SI-LABEL: {{^}}s_uint_to_fp_i64_to_f64
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22 define amdgpu_kernel void @s_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) {
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23 %cast = uitofp i64 %in to double
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24 store double %cast, double addrspace(1)* %out, align 8
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25 ret void
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26 }
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28 ; SI-LABEL: {{^}}s_uint_to_fp_v2i64_to_v2f64
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29 define amdgpu_kernel void @s_uint_to_fp_v2i64_to_v2f64(<2 x double> addrspace(1)* %out, <2 x i64> %in) {
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30 %cast = uitofp <2 x i64> %in to <2 x double>
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31 store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16
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32 ret void
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33 }
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34
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35 ; SI-LABEL: {{^}}s_uint_to_fp_v4i64_to_v4f64
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36 define amdgpu_kernel void @s_uint_to_fp_v4i64_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i64> %in) {
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37 %cast = uitofp <4 x i64> %in to <4 x double>
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38 store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16
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39 ret void
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40 }
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42 ; SI-LABEL: {{^}}s_uint_to_fp_i32_to_f64
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43 ; SI: v_cvt_f64_u32_e32
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44 ; SI: s_endpgm
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45 define amdgpu_kernel void @s_uint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) {
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46 %cast = uitofp i32 %in to double
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47 store double %cast, double addrspace(1)* %out, align 8
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48 ret void
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49 }
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50
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51 ; SI-LABEL: {{^}}s_uint_to_fp_v2i32_to_v2f64
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52 ; SI: v_cvt_f64_u32_e32
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53 ; SI: v_cvt_f64_u32_e32
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54 ; SI: s_endpgm
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55 define amdgpu_kernel void @s_uint_to_fp_v2i32_to_v2f64(<2 x double> addrspace(1)* %out, <2 x i32> %in) {
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56 %cast = uitofp <2 x i32> %in to <2 x double>
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57 store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16
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58 ret void
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59 }
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61 ; SI-LABEL: {{^}}s_uint_to_fp_v4i32_to_v4f64
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62 ; SI: v_cvt_f64_u32_e32
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63 ; SI: v_cvt_f64_u32_e32
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64 ; SI: v_cvt_f64_u32_e32
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65 ; SI: v_cvt_f64_u32_e32
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66 ; SI: s_endpgm
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67 define amdgpu_kernel void @s_uint_to_fp_v4i32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i32> %in) {
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68 %cast = uitofp <4 x i32> %in to <4 x double>
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69 store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16
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70 ret void
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71 }
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73 ; We can't fold the SGPRs into v_cndmask_b32_e32, because it already
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74 ; uses an SGPR (implicit vcc).
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75
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76 ; SI-LABEL: {{^}}uint_to_fp_i1_to_f64:
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77 ; SI-DAG: v_cmp_eq_u32_e64 vcc
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78 ; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}
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79 ; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
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80 ; SI: buffer_store_dwordx2 v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
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81 ; SI: s_endpgm
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82 define amdgpu_kernel void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) {
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83 %cmp = icmp eq i32 %in, 0
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84 %fp = uitofp i1 %cmp to double
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85 store double %fp, double addrspace(1)* %out, align 4
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86 ret void
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87 }
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89 ; SI-LABEL: {{^}}uint_to_fp_i1_to_f64_load:
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90 ; SI: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, 1
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91 ; SI-NEXT: v_cvt_f64_u32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
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92 ; SI: buffer_store_dwordx2 [[RESULT]]
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93 ; SI: s_endpgm
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94 define amdgpu_kernel void @uint_to_fp_i1_to_f64_load(double addrspace(1)* %out, i1 %in) {
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95 %fp = uitofp i1 %in to double
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96 store double %fp, double addrspace(1)* %out, align 8
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97 ret void
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98 }