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annotate test/CodeGen/Hexagon/isel-op-zext-i1.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
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121
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1 ; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
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2
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3 ; In the IR, the i1 value is zero-extended first, then passed to add.
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4 ; Check that in the final code, the mux happens after the add.
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5 ; CHECK: [[REG1:r[0-9]+]] = add([[REG0:r[0-9]+]],#1)
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6 ; CHECK: r{{[0-9]+}} = mux(p{{[0-3]}},[[REG1]],[[REG0]])
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7
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8 define i32 @foo(i32 %a, i32 %b) {
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9 %v0 = icmp eq i32 %a, %b
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10 %v1 = zext i1 %v0 to i32
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11 %v2 = add i32 %v1, %a
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12 ret i32 %v2
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13 }