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annotate test/MC/AMDGPU/sopk-err.s @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children 3a76565eade5
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120
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1 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN %s
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2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI %s
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3 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
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4
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5 s_setreg_b32 0x1f803, s2
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6 // GCN: error: invalid immediate: only 16-bit values are legal
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7
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8 s_setreg_b32 hwreg(0x40), s2
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9 // GCN: error: invalid code of hardware register: only 6-bit values are legal
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10
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11 s_setreg_b32 hwreg(HW_REG_WRONG), s2
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12 // GCN: error: invalid symbolic name of hardware register
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13
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14 s_setreg_b32 hwreg(3,32,32), s2
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15 // GCN: error: invalid bit offset: only 5-bit values are legal
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16
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17 s_setreg_b32 hwreg(3,0,33), s2
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18 // GCN: error: invalid bitfield width: only values from 1 to 32 are legal
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19
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20 s_setreg_imm32_b32 0x1f803, 0xff
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21 // GCN: error: invalid immediate: only 16-bit values are legal
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22
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23 s_setreg_imm32_b32 hwreg(3,0,33), 0xff
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24 // GCN: error: invalid bitfield width: only values from 1 to 32 are legal
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25
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26 s_getreg_b32 s2, hwreg(3,32,32)
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27 // GCN: error: invalid bit offset: only 5-bit values are legal
121
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28
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29 s_cmpk_le_u32 s2, -1
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30 // GCN: error: invalid operand for instruction
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31
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32 s_cmpk_le_u32 s2, 0x1ffff
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33 // GCN: error: invalid operand for instruction
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34
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35 s_cmpk_le_u32 s2, 0x10000
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36 // GCN: error: invalid operand for instruction
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37
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38 s_mulk_i32 s2, 0xFFFFFFFFFFFF0000
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39 // GCN: error: invalid operand for instruction
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40
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41 s_mulk_i32 s2, 0x10000
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42 // GCN: error: invalid operand for instruction