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annotate test/MC/Hexagon/v62a_regs.s @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
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121
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1 # RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V62
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2 # RUN: not llvm-mc -arch=hexagon -mcpu=hexagonv60 -filetype=asm %s 2>%t; FileCheck -check-prefix=CHECK-NOV62 %s < %t
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3 #
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4
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5 # Assure that v62 added registers are understood
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6
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7 r0=framelimit
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8 r0=framekey
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9 r1:0=c17:16
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10
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11 # CHECK-V62: 6a10c000 { r0 = framelimit }
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12 # CHECK-V62: 6a11c000 { r0 = framekey }
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13 # CHECK-V62: 6810c000 { r1:0 = c17:16 }
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14 # CHECK-NOV62: rror: invalid operand for instruction
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15 # CHECK-NOV62: rror: invalid operand for instruction
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16 # CHECK-NOV62: rror: invalid operand for instruction
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17
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18 r0=pktcountlo
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19 r0=pktcounthi
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20 r1:0=c19:18
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21 r1:0=pktcount
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22
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23 # CHECK-V62: 6a12c000 { r0 = pktcountlo }
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24 # CHECK-V62: 6a13c000 { r0 = pktcounthi }
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25 # CHECK-V62: 6812c000 { r1:0 = c19:18 }
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26 # CHECK-V62: 6812c000 { r1:0 = c19:18 }
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27 # CHECK-NOV62: rror: invalid operand for instruction
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28 # CHECK-NOV62: rror: invalid operand for instruction
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29 # CHECK-NOV62: rror: invalid operand for instruction
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30 # CHECK-NOV62: rror: invalid operand for instruction
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31
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32 r0=utimerlo
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33 r0=utimerhi
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34 r1:0=c31:30
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35 r1:0=UTIMER
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36
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37 # CHECK-V62: 6a1ec000 { r0 = utimerlo }
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38 # CHECK-V62: 6a1fc000 { r0 = utimerhi }
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39 # CHECK-V62: 681ec000 { r1:0 = c31:30 }
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40 # CHECK-V62: 681ec000 { r1:0 = c31:30 }
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41 # CHECK-NOV62: rror: invalid operand for instruction
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42 # CHECK-NOV62: rror: invalid operand for instruction
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43 # CHECK-NOV62: rror: invalid operand for instruction
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44 # CHECK-NOV62: rror: invalid operand for instruction