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annotate lib/Target/NVPTX/NVPTXISelDAGToDAG.h @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
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children 54457678186b
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1 //===-- NVPTXISelDAGToDAG.h - A dag to dag inst selector for NVPTX --------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines an instruction selector for the NVPTX target.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #define DEBUG_TYPE "nvptx-isel"
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15
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16 #include "NVPTX.h"
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17 #include "NVPTXISelLowering.h"
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18 #include "NVPTXRegisterInfo.h"
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19 #include "NVPTXTargetMachine.h"
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20 #include "llvm/CodeGen/SelectionDAGISel.h"
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21 #include "llvm/IR/Intrinsics.h"
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22 #include "llvm/Support/Compiler.h"
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23 using namespace llvm;
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24
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25 namespace {
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26
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27 class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
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28
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29 // If true, generate corresponding FPCONTRACT. This is
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30 // language dependent (i.e. CUDA and OpenCL works differently).
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31 bool doFMAF64;
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32 bool doFMAF32;
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33 bool doFMAF64AGG;
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34 bool doFMAF32AGG;
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35 bool allowFMA;
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36
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37 // If true, generate mul.wide from sext and mul
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38 bool doMulWide;
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39
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40 int getDivF32Level() const;
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41 bool usePrecSqrtF32() const;
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42 bool useF32FTZ() const;
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43
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44 public:
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45 explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
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46 CodeGenOpt::Level OptLevel);
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47
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48 // Pass Name
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49 virtual const char *getPassName() const {
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50 return "NVPTX DAG->DAG Pattern Instruction Selection";
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51 }
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52
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53 const NVPTXSubtarget &Subtarget;
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54
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55 virtual bool SelectInlineAsmMemoryOperand(
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56 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps);
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57 private:
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58 // Include the pieces autogenerated from the target description.
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59 #include "NVPTXGenDAGISel.inc"
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60
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61 SDNode *Select(SDNode *N);
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62 SDNode *SelectLoad(SDNode *N);
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63 SDNode *SelectLoadVector(SDNode *N);
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64 SDNode *SelectLDGLDUVector(SDNode *N);
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65 SDNode *SelectStore(SDNode *N);
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66 SDNode *SelectStoreVector(SDNode *N);
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67 SDNode *SelectLoadParam(SDNode *N);
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68 SDNode *SelectStoreRetval(SDNode *N);
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69 SDNode *SelectStoreParam(SDNode *N);
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70
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71 inline SDValue getI32Imm(unsigned Imm) {
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72 return CurDAG->getTargetConstant(Imm, MVT::i32);
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73 }
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74
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75 // Match direct address complex pattern.
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76 bool SelectDirectAddr(SDValue N, SDValue &Address);
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77
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78 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
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79 SDValue &Offset, MVT mvt);
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80 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
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81 SDValue &Offset);
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82 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
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83 SDValue &Offset);
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84
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85 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
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86 SDValue &Offset, MVT mvt);
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87 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
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88 SDValue &Offset);
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89 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
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90 SDValue &Offset);
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91
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92 bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
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93
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94 bool UndefOrImm(SDValue Op, SDValue N, SDValue &Retval);
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95
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96 };
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97 }