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annotate lib/Target/PowerPC/PPCScheduleG4Plus.td @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
parents
children e4204d083e25
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1 //===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the itinerary class data for the G4+ (7450) processor.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 def IU3 : FuncUnit; // integer unit 3 (7450 simple)
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15 def IU4 : FuncUnit; // integer unit 4 (7450 simple)
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16
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17 def G4PlusItineraries : ProcessorItineraries<
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18 [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [
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19 InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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20 InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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21 InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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22 InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>,
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23 InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>,
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24 InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>,
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25 InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
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26 InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>,
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27 InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>,
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28 InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>,
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29 InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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30 InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
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31 InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
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32 InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
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33 InstrItinData<BrCR , [InstrStage<2, [IU2]>]>,
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34 InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>,
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35 InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>,
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36 InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
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37 InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
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38 InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>,
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39 InstrItinData<LdStLoadUpd , [InstrStage<3, [SLU]>]>,
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40 InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>,
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41 InstrItinData<LdStStoreUpd, [InstrStage<3, [SLU]>]>,
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42 InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>,
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43 InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>,
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44 InstrItinData<LdStSTFD , [InstrStage<3, [SLU]>]>,
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45 InstrItinData<LdStSTFDU , [InstrStage<3, [SLU]>]>,
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46 InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>,
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47 InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>,
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48 InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>,
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49 InstrItinData<LdStLHAU , [InstrStage<3, [SLU]>]>,
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50 InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>,
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51 InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
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52 InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>,
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53 InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
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54 InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
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55 InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>,
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56 InstrItinData<LdStSTDU , [InstrStage<3, [SLU]>]>,
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57 InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>,
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58 InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>,
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59 InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
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60 InstrItinData<SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
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61 InstrItinData<SprMFSR , [InstrStage<4, [IU2]>]>,
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62 InstrItinData<SprMTMSR , [InstrStage<2, [IU2]>]>,
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63 InstrItinData<SprMTSR , [InstrStage<2, [IU2]>]>,
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64 InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>,
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65 InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>,
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66 InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>,
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67 InstrItinData<SprMFSPR , [InstrStage<4, [IU2]>]>,
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68 InstrItinData<SprMFTB , [InstrStage<5, [IU2]>]>,
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69 InstrItinData<SprMTSPR , [InstrStage<2, [IU2]>]>,
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70 InstrItinData<SprMTSRIN , [InstrStage<2, [IU2]>]>,
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71 InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
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72 InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
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73 InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>,
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74 InstrItinData<FPAddSub , [InstrStage<5, [FPU1]>]>,
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75 InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>,
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76 InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>,
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77 InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>,
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78 InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>,
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79 InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>,
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80 InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
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81 InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
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82 InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
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83 InstrItinData<VecComplex , [InstrStage<4, [VIU2]>]>,
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84 InstrItinData<VecPerm , [InstrStage<2, [VPU]>]>,
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85 InstrItinData<VecFPRound , [InstrStage<4, [VIU1]>]>,
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86 InstrItinData<VecVSL , [InstrStage<2, [VPU]>]>,
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87 InstrItinData<VecVSR , [InstrStage<2, [VPU]>]>
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88 ]>;