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annotate lib/Target/SystemZ/SystemZInstrInfo.h @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
parents
children 54457678186b
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1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
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15 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
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16
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17 #include "SystemZ.h"
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18 #include "SystemZRegisterInfo.h"
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19 #include "llvm/Target/TargetInstrInfo.h"
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20
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21 #define GET_INSTRINFO_HEADER
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22 #include "SystemZGenInstrInfo.inc"
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23
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24 namespace llvm {
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25
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26 class SystemZTargetMachine;
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27
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28 namespace SystemZII {
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29 enum {
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30 // See comments in SystemZInstrFormats.td.
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31 SimpleBDXLoad = (1 << 0),
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32 SimpleBDXStore = (1 << 1),
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33 Has20BitOffset = (1 << 2),
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34 HasIndex = (1 << 3),
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35 Is128Bit = (1 << 4),
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36 AccessSizeMask = (31 << 5),
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37 AccessSizeShift = 5,
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38 CCValuesMask = (15 << 10),
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39 CCValuesShift = 10,
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40 CompareZeroCCMaskMask = (15 << 14),
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41 CompareZeroCCMaskShift = 14,
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42 CCMaskFirst = (1 << 18),
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43 CCMaskLast = (1 << 19),
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44 IsLogical = (1 << 20)
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45 };
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46 static inline unsigned getAccessSize(unsigned int Flags) {
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47 return (Flags & AccessSizeMask) >> AccessSizeShift;
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48 }
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49 static inline unsigned getCCValues(unsigned int Flags) {
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50 return (Flags & CCValuesMask) >> CCValuesShift;
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51 }
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52 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
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53 return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
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54 }
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55
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56 // SystemZ MachineOperand target flags.
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57 enum {
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58 // Masks out the bits for the access model.
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59 MO_SYMBOL_MODIFIER = (1 << 0),
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60
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61 // @GOT (aka @GOTENT)
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62 MO_GOT = (1 << 0)
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63 };
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64 // Classifies a branch.
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65 enum BranchType {
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66 // An instruction that branches on the current value of CC.
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67 BranchNormal,
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68
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69 // An instruction that peforms a 32-bit signed comparison and branches
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70 // on the result.
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71 BranchC,
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72
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73 // An instruction that peforms a 32-bit unsigned comparison and branches
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74 // on the result.
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75 BranchCL,
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76
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77 // An instruction that peforms a 64-bit signed comparison and branches
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78 // on the result.
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79 BranchCG,
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80
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81 // An instruction that peforms a 64-bit unsigned comparison and branches
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82 // on the result.
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83 BranchCLG,
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84
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85 // An instruction that decrements a 32-bit register and branches if
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86 // the result is nonzero.
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87 BranchCT,
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88
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89 // An instruction that decrements a 64-bit register and branches if
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90 // the result is nonzero.
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91 BranchCTG
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92 };
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93 // Information about a branch instruction.
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94 struct Branch {
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95 // The type of the branch.
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96 BranchType Type;
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97
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98 // CCMASK_<N> is set if CC might be equal to N.
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99 unsigned CCValid;
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100
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101 // CCMASK_<N> is set if the branch should be taken when CC == N.
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102 unsigned CCMask;
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103
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104 // The target of the branch.
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105 const MachineOperand *Target;
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106
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107 Branch(BranchType type, unsigned ccValid, unsigned ccMask,
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108 const MachineOperand *target)
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109 : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
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110 };
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111 }
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112
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113 class SystemZInstrInfo : public SystemZGenInstrInfo {
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114 const SystemZRegisterInfo RI;
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115 SystemZTargetMachine &TM;
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116
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117 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
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118 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
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119 void expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
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120 unsigned HighOpcode, bool ConvertHigh) const;
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121 void expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
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122 unsigned LowOpcodeK, unsigned HighOpcode) const;
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123 void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
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124 unsigned HighOpcode) const;
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125 void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
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126 unsigned Size) const;
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127 void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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128 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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129 unsigned LowLowOpcode, unsigned Size, bool KillSrc) const;
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130 virtual void anchor();
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131
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132 public:
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133 explicit SystemZInstrInfo(SystemZTargetMachine &TM);
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134
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135 // Override TargetInstrInfo.
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136 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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137 int &FrameIndex) const LLVM_OVERRIDE;
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138 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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139 int &FrameIndex) const LLVM_OVERRIDE;
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140 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
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141 int &SrcFrameIndex) const LLVM_OVERRIDE;
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142 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
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143 MachineBasicBlock *&TBB,
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144 MachineBasicBlock *&FBB,
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145 SmallVectorImpl<MachineOperand> &Cond,
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146 bool AllowModify) const LLVM_OVERRIDE;
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147 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
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148 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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149 MachineBasicBlock *FBB,
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150 const SmallVectorImpl<MachineOperand> &Cond,
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151 DebugLoc DL) const LLVM_OVERRIDE;
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152 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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153 unsigned &SrcReg2, int &Mask, int &Value) const
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154 LLVM_OVERRIDE;
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155 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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156 unsigned SrcReg2, int Mask, int Value,
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157 const MachineRegisterInfo *MRI) const LLVM_OVERRIDE;
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158 virtual bool isPredicable(MachineInstr *MI) const LLVM_OVERRIDE;
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159 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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160 unsigned ExtraPredCycles,
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161 const BranchProbability &Probability) const
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162 LLVM_OVERRIDE;
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163 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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164 unsigned NumCyclesT,
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165 unsigned ExtraPredCyclesT,
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166 MachineBasicBlock &FMBB,
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167 unsigned NumCyclesF,
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168 unsigned ExtraPredCyclesF,
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169 const BranchProbability &Probability) const
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170 LLVM_OVERRIDE;
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171 virtual bool
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172 PredicateInstruction(MachineInstr *MI,
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173 const SmallVectorImpl<MachineOperand> &Pred) const
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174 LLVM_OVERRIDE;
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175 virtual void copyPhysReg(MachineBasicBlock &MBB,
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176 MachineBasicBlock::iterator MBBI, DebugLoc DL,
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177 unsigned DestReg, unsigned SrcReg,
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178 bool KillSrc) const LLVM_OVERRIDE;
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179 virtual void
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180 storeRegToStackSlot(MachineBasicBlock &MBB,
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diff changeset
181 MachineBasicBlock::iterator MBBI,
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diff changeset
182 unsigned SrcReg, bool isKill, int FrameIndex,
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diff changeset
183 const TargetRegisterClass *RC,
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184 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
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185 virtual void
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diff changeset
186 loadRegFromStackSlot(MachineBasicBlock &MBB,
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187 MachineBasicBlock::iterator MBBI,
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diff changeset
188 unsigned DestReg, int FrameIdx,
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diff changeset
189 const TargetRegisterClass *RC,
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190 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
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191 virtual MachineInstr *
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diff changeset
192 convertToThreeAddress(MachineFunction::iterator &MFI,
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diff changeset
193 MachineBasicBlock::iterator &MBBI,
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diff changeset
194 LiveVariables *LV) const;
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195 virtual MachineInstr *
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196 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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diff changeset
197 const SmallVectorImpl<unsigned> &Ops,
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198 int FrameIndex) const;
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199 virtual MachineInstr *
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200 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
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diff changeset
201 const SmallVectorImpl<unsigned> &Ops,
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diff changeset
202 MachineInstr* LoadMI) const;
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diff changeset
203 virtual bool
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diff changeset
204 expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
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diff changeset
205 virtual bool
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diff changeset
206 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
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diff changeset
207 LLVM_OVERRIDE;
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diff changeset
208
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diff changeset
209 // Return the SystemZRegisterInfo, which this class owns.
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diff changeset
210 const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
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diff changeset
211
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diff changeset
212 // Return the size in bytes of MI.
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diff changeset
213 uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
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diff changeset
214
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diff changeset
215 // Return true if MI is a conditional or unconditional branch.
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diff changeset
216 // When returning true, set Cond to the mask of condition-code
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diff changeset
217 // values on which the instruction will branch, and set Target
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diff changeset
218 // to the operand that contains the branch target. This target
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diff changeset
219 // can be a register or a basic block.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff changeset
220 SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
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diff changeset
221
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diff changeset
222 // Get the load and store opcodes for a given register class.
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parents:
diff changeset
223 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
224 unsigned &LoadOpcode, unsigned &StoreOpcode) const;
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diff changeset
225
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226 // Opcode is the opcode of an instruction that has an address operand,
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diff changeset
227 // and the caller wants to perform that instruction's operation on an
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diff changeset
228 // address that has displacement Offset. Return the opcode of a suitable
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diff changeset
229 // instruction (which might be Opcode itself) or 0 if no such instruction
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diff changeset
230 // exists.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
231 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
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diff changeset
232
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diff changeset
233 // If Opcode is a load instruction that has a LOAD AND TEST form,
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diff changeset
234 // return the opcode for the testing form, otherwise return 0.
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parents:
diff changeset
235 unsigned getLoadAndTest(unsigned Opcode) const;
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diff changeset
236
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diff changeset
237 // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
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parents:
diff changeset
238 // Mask of the R2 operand, given that only the low BitSize bits of Mask are
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
239 // significant. Set Start and End to the I3 and I4 operands if so.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
240 bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
241 unsigned &Start, unsigned &End) const;
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parents:
diff changeset
242
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parents:
diff changeset
243 // If Opcode is a COMPARE opcode for which an associated COMPARE AND
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
244 // BRANCH exists, return the opcode for the latter, otherwise return 0.
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parents:
diff changeset
245 // MI, if nonnull, is the compare instruction.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
246 unsigned getCompareAndBranch(unsigned Opcode,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
247 const MachineInstr *MI = 0) const;
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parents:
diff changeset
248
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diff changeset
249 // Emit code before MBBI in MI to move immediate value Value into
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parents:
diff changeset
250 // physical register Reg.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 void loadImmediate(MachineBasicBlock &MBB,
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parents:
diff changeset
252 MachineBasicBlock::iterator MBBI,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 unsigned Reg, uint64_t Value) const;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff changeset
254 };
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diff changeset
255 } // end namespace llvm
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diff changeset
256
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diff changeset
257 #endif