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annotate lib/Target/XCore/XCoreInstrInfo.h @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
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children 54457678186b
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1 //===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the XCore implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef XCOREINSTRUCTIONINFO_H
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15 #define XCOREINSTRUCTIONINFO_H
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16
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17 #include "XCoreRegisterInfo.h"
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18 #include "llvm/Target/TargetInstrInfo.h"
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19
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20 #define GET_INSTRINFO_HEADER
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21 #include "XCoreGenInstrInfo.inc"
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22
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23 namespace llvm {
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24
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25 class XCoreInstrInfo : public XCoreGenInstrInfo {
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26 const XCoreRegisterInfo RI;
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27 virtual void anchor();
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28 public:
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29 XCoreInstrInfo();
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30
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31 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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32 /// such, whenever a client has an instance of instruction info, it should
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33 /// always be able to get register info as well (through this method).
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34 ///
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35 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
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36
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37 /// isLoadFromStackSlot - If the specified machine instruction is a direct
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38 /// load from a stack slot, return the virtual or physical register number of
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39 /// the destination along with the FrameIndex of the loaded stack slot. If
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40 /// not, return 0. This predicate must return 0 if the instruction has
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41 /// any side effects other than loading from the stack slot.
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42 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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43 int &FrameIndex) const;
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44
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45 /// isStoreToStackSlot - If the specified machine instruction is a direct
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46 /// store to a stack slot, return the virtual or physical register number of
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47 /// the source reg along with the FrameIndex of the loaded stack slot. If
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48 /// not, return 0. This predicate must return 0 if the instruction has
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49 /// any side effects other than storing to the stack slot.
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50 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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51 int &FrameIndex) const;
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52
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53 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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54 MachineBasicBlock *&FBB,
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55 SmallVectorImpl<MachineOperand> &Cond,
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56 bool AllowModify) const;
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57
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58 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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59 MachineBasicBlock *FBB,
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60 const SmallVectorImpl<MachineOperand> &Cond,
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61 DebugLoc DL) const;
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62
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63 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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64
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65 virtual void copyPhysReg(MachineBasicBlock &MBB,
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66 MachineBasicBlock::iterator I, DebugLoc DL,
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67 unsigned DestReg, unsigned SrcReg,
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68 bool KillSrc) const;
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69
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70 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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71 MachineBasicBlock::iterator MI,
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72 unsigned SrcReg, bool isKill, int FrameIndex,
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73 const TargetRegisterClass *RC,
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74 const TargetRegisterInfo *TRI) const;
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75
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76 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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77 MachineBasicBlock::iterator MI,
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78 unsigned DestReg, int FrameIndex,
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79 const TargetRegisterClass *RC,
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80 const TargetRegisterInfo *TRI) const;
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81
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82 virtual bool ReverseBranchCondition(
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83 SmallVectorImpl<MachineOperand> &Cond) const;
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84 };
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85
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86 }
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87
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88 #endif