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annotate lib/Target/ARM/ARMBaseInstrInfo.h @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 60c9769439b8
children 1172e4bd9c6f
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1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
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15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
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16
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17 #include "MCTargetDesc/ARMBaseInfo.h"
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18 #include "llvm/ADT/DenseMap.h"
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19 #include "llvm/ADT/SmallSet.h"
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20 #include "llvm/CodeGen/MachineInstrBuilder.h"
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21 #include "llvm/Support/CodeGen.h"
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22 #include "llvm/Target/TargetInstrInfo.h"
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23
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24 #define GET_INSTRINFO_HEADER
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25 #include "ARMGenInstrInfo.inc"
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26
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27 namespace llvm {
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28 class ARMSubtarget;
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29 class ARMBaseRegisterInfo;
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30
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31 class ARMBaseInstrInfo : public ARMGenInstrInfo {
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32 const ARMSubtarget &Subtarget;
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33
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34 protected:
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35 // Can be only subclassed.
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36 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
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37
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38 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
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39 unsigned LoadImmOpc, unsigned LoadOpc,
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40 Reloc::Model RM) const;
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41
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42 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
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43 /// and \p DefIdx.
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44 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
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45 /// the list is modeled as <Reg:SubReg, SubIdx>.
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46 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
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47 /// two elements:
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48 /// - vreg1:sub1, sub0
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49 /// - vreg2<:0>, sub1
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50 ///
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51 /// \returns true if it is possible to build such an input sequence
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52 /// with the pair \p MI, \p DefIdx. False otherwise.
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53 ///
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54 /// \pre MI.isRegSequenceLike().
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55 bool getRegSequenceLikeInputs(
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56 const MachineInstr &MI, unsigned DefIdx,
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57 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
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58
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59 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
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60 /// and \p DefIdx.
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61 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
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62 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
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63 /// - vreg1:sub1, sub0
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64 ///
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65 /// \returns true if it is possible to build such an input sequence
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66 /// with the pair \p MI, \p DefIdx. False otherwise.
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67 ///
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68 /// \pre MI.isExtractSubregLike().
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69 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
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70 RegSubRegPairAndIdx &InputReg) const override;
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71
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72 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
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73 /// and \p DefIdx.
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74 /// \p [out] BaseReg and \p [out] InsertedReg contain
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75 /// the equivalent inputs of INSERT_SUBREG.
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76 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
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77 /// - BaseReg: vreg0:sub0
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78 /// - InsertedReg: vreg1:sub1, sub3
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79 ///
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80 /// \returns true if it is possible to build such an input sequence
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81 /// with the pair \p MI, \p DefIdx. False otherwise.
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82 ///
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83 /// \pre MI.isInsertSubregLike().
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84 bool
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85 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
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86 RegSubRegPair &BaseReg,
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87 RegSubRegPairAndIdx &InsertedReg) const override;
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88
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89 /// Commutes the operands in the given instruction.
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90 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
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91 ///
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92 /// Do not call this method for a non-commutable instruction or for
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93 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
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94 /// Even though the instruction is commutable, the method may still
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95 /// fail to commute the operands, null pointer is returned in such cases.
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96 MachineInstr *commuteInstructionImpl(MachineInstr *MI,
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97 bool NewMI,
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98 unsigned OpIdx1,
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99 unsigned OpIdx2) const override;
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100
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101 public:
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102 // Return whether the target has an explicit NOP encoding.
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103 bool hasNOP() const;
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104
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105 // Return the non-pre/post incrementing version of 'Opc'. Return 0
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106 // if there is not such an opcode.
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107 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
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108
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109 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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110 MachineBasicBlock::iterator &MBBI,
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111 LiveVariables *LV) const override;
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112
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113 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
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114 const ARMSubtarget &getSubtarget() const { return Subtarget; }
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115
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116 ScheduleHazardRecognizer *
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117 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
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118 const ScheduleDAG *DAG) const override;
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119
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120 ScheduleHazardRecognizer *
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121 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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122 const ScheduleDAG *DAG) const override;
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123
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124 // Branch analysis.
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125 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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126 MachineBasicBlock *&FBB,
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127 SmallVectorImpl<MachineOperand> &Cond,
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128 bool AllowModify = false) const override;
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129 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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130 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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131 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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132 DebugLoc DL) const override;
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133
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134 bool
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135 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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136
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137 // Predication support.
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138 bool isPredicated(const MachineInstr *MI) const override;
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139
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140 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
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141 int PIdx = MI->findFirstPredOperandIdx();
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142 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
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143 : ARMCC::AL;
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144 }
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145
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146 bool PredicateInstruction(MachineInstr *MI,
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147 ArrayRef<MachineOperand> Pred) const override;
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148
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149 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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150 ArrayRef<MachineOperand> Pred2) const override;
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151
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152 bool DefinesPredicate(MachineInstr *MI,
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153 std::vector<MachineOperand> &Pred) const override;
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154
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155 bool isPredicable(MachineInstr *MI) const override;
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156
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157 /// GetInstSize - Returns the size of the specified MachineInstr.
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158 ///
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159 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
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160
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161 unsigned isLoadFromStackSlot(const MachineInstr *MI,
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162 int &FrameIndex) const override;
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163 unsigned isStoreToStackSlot(const MachineInstr *MI,
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164 int &FrameIndex) const override;
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165 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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166 int &FrameIndex) const override;
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167 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
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168 int &FrameIndex) const override;
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169
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170 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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171 unsigned SrcReg, bool KillSrc,
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172 const ARMSubtarget &Subtarget) const;
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173 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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174 unsigned DestReg, bool KillSrc,
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175 const ARMSubtarget &Subtarget) const;
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176
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177 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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178 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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179 bool KillSrc) const override;
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180
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181 void storeRegToStackSlot(MachineBasicBlock &MBB,
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182 MachineBasicBlock::iterator MBBI,
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183 unsigned SrcReg, bool isKill, int FrameIndex,
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184 const TargetRegisterClass *RC,
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185 const TargetRegisterInfo *TRI) const override;
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186
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187 void loadRegFromStackSlot(MachineBasicBlock &MBB,
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188 MachineBasicBlock::iterator MBBI,
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189 unsigned DestReg, int FrameIndex,
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190 const TargetRegisterClass *RC,
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191 const TargetRegisterInfo *TRI) const override;
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192
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193 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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194
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195 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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196 unsigned DestReg, unsigned SubIdx,
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197 const MachineInstr *Orig,
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198 const TargetRegisterInfo &TRI) const override;
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199
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200 MachineInstr *duplicate(MachineInstr *Orig,
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201 MachineFunction &MF) const override;
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202
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203 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
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204 unsigned SubIdx, unsigned State,
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205 const TargetRegisterInfo *TRI) const;
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206
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207 bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1,
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208 const MachineRegisterInfo *MRI) const override;
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209
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210 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
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211 /// determine if two loads are loading from the same base address. It should
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212 /// only return true if the base pointers are the same and the only
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213 /// differences between the two addresses is the offset. It also returns the
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214 /// offsets by reference.
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215 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
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216 int64_t &Offset2) const override;
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217
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218 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
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219 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
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220 /// should be scheduled togther. On some targets if two loads are loading from
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221 /// addresses in the same cache line, it's better if they are scheduled
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222 /// together. This function takes two integers that represent the load offsets
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223 /// from the common base address. It returns true if it decides it's desirable
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224 /// to schedule the two loads together. "NumLoads" is the number of loads that
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225 /// have already been scheduled after Load1.
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226 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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227 int64_t Offset1, int64_t Offset2,
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228 unsigned NumLoads) const override;
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229
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230 bool isSchedulingBoundary(const MachineInstr *MI,
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231 const MachineBasicBlock *MBB,
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232 const MachineFunction &MF) const override;
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233
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234 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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235 unsigned NumCycles, unsigned ExtraPredCycles,
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236 BranchProbability Probability) const override;
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237
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238 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
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239 unsigned ExtraT, MachineBasicBlock &FMBB,
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240 unsigned NumF, unsigned ExtraF,
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241 BranchProbability Probability) const override;
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242
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243 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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244 BranchProbability Probability) const override {
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245 return NumCycles == 1;
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246 }
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247
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248 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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249 MachineBasicBlock &FMBB) const override;
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250
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251 /// analyzeCompare - For a comparison instruction, return the source registers
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252 /// in SrcReg and SrcReg2 if having two register operands, and the value it
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253 /// compares against in CmpValue. Return true if the comparison instruction
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254 /// can be analyzed.
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255 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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256 unsigned &SrcReg2, int &CmpMask,
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257 int &CmpValue) const override;
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258
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259 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
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260 /// that we can remove a "comparison with zero"; Remove a redundant CMP
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261 /// instruction if the flags can be updated in the same way by an earlier
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262 /// instruction such as SUB.
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263 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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264 unsigned SrcReg2, int CmpMask, int CmpValue,
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265 const MachineRegisterInfo *MRI) const override;
0
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266
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267 bool analyzeSelect(const MachineInstr *MI,
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268 SmallVectorImpl<MachineOperand> &Cond,
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269 unsigned &TrueOp, unsigned &FalseOp,
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270 bool &Optimizable) const override;
0
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271
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272 MachineInstr *optimizeSelect(MachineInstr *MI,
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273 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
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274 bool) const override;
0
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275
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276 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
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277 /// instruction, try to fold the immediate into the use instruction.
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278 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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279 unsigned Reg, MachineRegisterInfo *MRI) const override;
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280
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281 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
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282 const MachineInstr *MI) const override;
0
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283
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284 int getOperandLatency(const InstrItineraryData *ItinData,
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285 const MachineInstr *DefMI, unsigned DefIdx,
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286 const MachineInstr *UseMI,
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287 unsigned UseIdx) const override;
0
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288 int getOperandLatency(const InstrItineraryData *ItinData,
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289 SDNode *DefNode, unsigned DefIdx,
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290 SDNode *UseNode, unsigned UseIdx) const override;
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291
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292 /// VFP/NEON execution domains.
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293 std::pair<uint16_t, uint16_t>
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294 getExecutionDomain(const MachineInstr *MI) const override;
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295 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
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296
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297 unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
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298 const TargetRegisterInfo*) const override;
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299 void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
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300 const TargetRegisterInfo *TRI) const override;
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301
0
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302 /// Get the number of addresses by LDM or VLDM or zero for unknown.
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303 unsigned getNumLDMAddresses(const MachineInstr *MI) const;
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304
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305 private:
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306 unsigned getInstBundleLength(const MachineInstr *MI) const;
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307
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308 int getVLDMDefCycle(const InstrItineraryData *ItinData,
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309 const MCInstrDesc &DefMCID,
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310 unsigned DefClass,
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311 unsigned DefIdx, unsigned DefAlign) const;
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312 int getLDMDefCycle(const InstrItineraryData *ItinData,
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313 const MCInstrDesc &DefMCID,
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314 unsigned DefClass,
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315 unsigned DefIdx, unsigned DefAlign) const;
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diff changeset
316 int getVSTMUseCycle(const InstrItineraryData *ItinData,
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317 const MCInstrDesc &UseMCID,
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318 unsigned UseClass,
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319 unsigned UseIdx, unsigned UseAlign) const;
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320 int getSTMUseCycle(const InstrItineraryData *ItinData,
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321 const MCInstrDesc &UseMCID,
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322 unsigned UseClass,
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323 unsigned UseIdx, unsigned UseAlign) const;
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324 int getOperandLatency(const InstrItineraryData *ItinData,
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325 const MCInstrDesc &DefMCID,
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326 unsigned DefIdx, unsigned DefAlign,
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327 const MCInstrDesc &UseMCID,
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328 unsigned UseIdx, unsigned UseAlign) const;
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329
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330 unsigned getPredicationCost(const MachineInstr *MI) const override;
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331
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332 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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333 const MachineInstr *MI,
77
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diff changeset
334 unsigned *PredCost = nullptr) const override;
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diff changeset
335
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336 int getInstrLatency(const InstrItineraryData *ItinData,
77
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diff changeset
337 SDNode *Node) const override;
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diff changeset
338
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diff changeset
339 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
0
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340 const MachineRegisterInfo *MRI,
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341 const MachineInstr *DefMI, unsigned DefIdx,
77
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342 const MachineInstr *UseMI,
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343 unsigned UseIdx) const override;
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344 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
77
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diff changeset
345 const MachineInstr *DefMI,
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346 unsigned DefIdx) const override;
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347
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348 /// verifyInstruction - Perform target specific instruction verification.
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diff changeset
349 bool verifyInstruction(const MachineInstr *MI,
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diff changeset
350 StringRef &ErrInfo) const override;
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diff changeset
351
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diff changeset
352 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI,
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diff changeset
353 Reloc::Model RM) const = 0;
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354
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diff changeset
355 void expandMEMCPY(MachineBasicBlock::iterator) const;
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diff changeset
356
0
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357 private:
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358 /// Modeling special VFP / NEON fp MLA / MLS hazards.
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diff changeset
359
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diff changeset
360 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
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361 /// MLx table.
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diff changeset
362 DenseMap<unsigned, unsigned> MLxEntryMap;
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diff changeset
363
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diff changeset
364 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
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365 /// stalls when scheduled together with fp MLA / MLS opcodes.
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366 SmallSet<unsigned, 16> MLxHazardOpcodes;
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diff changeset
367
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368 public:
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369 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
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370 /// instruction.
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diff changeset
371 bool isFpMLxInstruction(unsigned Opcode) const {
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372 return MLxEntryMap.count(Opcode);
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373 }
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diff changeset
374
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375 /// isFpMLxInstruction - This version also returns the multiply opcode and the
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376 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
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377 /// the MLX instructions with an extra lane operand.
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diff changeset
378 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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diff changeset
379 unsigned &AddSubOpc, bool &NegAcc,
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diff changeset
380 bool &HasLane) const;
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diff changeset
381
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382 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
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diff changeset
383 /// will cause stalls when scheduled after (within 4-cycle window) a fp
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parents:
diff changeset
384 /// MLA / MLS instruction.
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diff changeset
385 bool canCauseFpMLxStall(unsigned Opcode) const {
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diff changeset
386 return MLxHazardOpcodes.count(Opcode);
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diff changeset
387 }
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diff changeset
388
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
389 /// Returns true if the instruction has a shift by immediate that can be
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
390 /// executed in one cycle less.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
391 bool isSwiftFastImmShift(const MachineInstr *MI) const;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
392 };
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
393
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
394 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
395 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
396 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
397 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
398
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
399 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
400 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
401 return MIB.addReg(0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
402 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
403
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
404 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
405 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
406 bool isDead = false) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
407 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
408 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
409
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
410 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
411 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
412 return MIB.addReg(0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
413 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
414
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
415 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
416 bool isUncondBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
417 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
418 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
419
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
420 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
421 bool isCondBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
422 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
423 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
424
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
425 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
426 bool isJumpTableBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
427 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
428 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
429 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
430
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
431 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
432 bool isIndirectBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
433 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
434 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
435
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
436 static inline bool isPopOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
437 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
438 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
439 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
440 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
441
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
442 static inline bool isPushOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
443 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
444 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
445 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
446
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
447 /// getInstrPredicate - If instruction is predicated, returns its predicate
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
448 /// condition, otherwise returns AL. It also returns the condition code
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
449 /// register by reference.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
450 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
451
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
452 unsigned getMatchingCondBranchOpcode(unsigned Opc);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
453
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
454 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
455 /// opcode of the SSA instruction representing the conditional MI.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
456 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
457 MachineInstr *&MI,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
458 const MachineRegisterInfo &MRI);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
459
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
460 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
461 /// the instruction is encoded with an 'S' bit is determined by the optional
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
462 /// CPSR def operand.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
463 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
464
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
465 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
466 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
467 /// code.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
468 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
469 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
470 unsigned DestReg, unsigned BaseReg, int NumBytes,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
471 ARMCC::CondCodes Pred, unsigned PredReg,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
472 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
473
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
474 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
475 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
476 unsigned DestReg, unsigned BaseReg, int NumBytes,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
477 ARMCC::CondCodes Pred, unsigned PredReg,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
478 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
479 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
480 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
481 unsigned DestReg, unsigned BaseReg,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
482 int NumBytes, const TargetInstrInfo &TII,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
483 const ARMBaseRegisterInfo& MRI,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
484 unsigned MIFlags = 0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
485
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
486 /// Tries to add registers to the reglist of a given base-updating
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
487 /// push/pop instruction to adjust the stack by an additional
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
488 /// NumBytes. This can save a few bytes per function in code-size, but
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
489 /// obviously generates more memory traffic. As such, it only takes
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
490 /// effect in functions being optimised for size.
33
e4204d083e25 LLVM 3.5
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
491 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
e4204d083e25 LLVM 3.5
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
492 MachineFunction &MF, MachineInstr *MI,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
493 unsigned NumBytes);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
494
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
495 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
496 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
497 /// offset could not be handled directly in MI, and return the left-over
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
498 /// portion by reference.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
499 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
500 unsigned FrameReg, int &Offset,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
501 const ARMBaseInstrInfo &TII);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
502
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
503 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
504 unsigned FrameReg, int &Offset,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
505 const ARMBaseInstrInfo &TII);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
506
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
507 } // End llvm namespace
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
508
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
509 #endif